Mr. Lin, Yaojian holds B.S. degree in Metal Materials & Heat Treatment from Huazhong University of Science and Technology with Honor of Outstanding Graduate, M.S. degree in Composite Materials from Shanghai Jiaotong University, and M.S. degree in Materials Science from University of Rochester, NY, United States. He once worked at Shanghai Jiaotong University, Lucent Bell Labs/Sychip, and STATS ChipPAC (Singapore), and is now VP of Corporate & GM of Technology R&D Center. He has over 20 years R&D and Technology Transfer Experience in Materials and Semiconductor Packaging development, especially in wafer level package and advanced packaging. He has hands-on experiences in end-to-end technology & product development from conceptual to high volume manufacturing in IPD, Wafer Bumping, WLCSP, eWLB/eWLCSP, 2.5D Fan-out & fcBGA, fcCSP and advanced SiP. He is the inventor/co-inventor of 200+ granted US patents in semiconductor packaging.
CET Group is a leading global semiconductor system integration packaging and test provider, offering a full range of turnkey services that include semiconductor package integration design and characterization, R&D, wafer probe, wafer bumping, package assembly, final test and drop shipment to vendors around the world.
Our comprehensive portfolio covers a wide spectrum of semiconductor applications such as mobile, communication, compute, consumer, automotive and industry etc., through advanced wafer level packaging, 2.5D/3D, System-in-Packaging and reliable flip chip and wire bonding technologies. JCET Group has two R&D centers in China and Korea, six manufacturing locations in China, Korea and Singapore, and sales centers around the world, providing close technology collaboration and efficient supply-chain manufacturing to customers in China and around the world.
通过高集成度的晶圆级WLP、2.5D / 3D、系统级（SiP）封装技术和高性能的Flip Chip和引线互联封装技术，长电科技的产品和技术涵盖了主流集成电路系统应用，包括网络通讯、移动终端、高性能计算、车载电子、大数据存储、人工智能与物联
网、工业智造等领域。 在中国、韩国拥有两大研发中心，在中国、韩国及新加坡拥有六大集成电路成品生产基地， 营销办事处分布于世界各地，可与全球客户进行紧密的技术合作并提供高效的产业链支持。