14:05 – 14:50
Moderator
Hamid Azimi, Ph.D.
International Semiconductor Industry Group (I.S.I.G.)
Dr Hamid Azimi, formerly Corporate VP, Director of Substrate Packaging TD of Intel. He was responsible for advanced substrate packaging for all Intel logic products across substrate suppliers’ factories, as well as the company’s two internal substrate R&D factories. These R&D factories are the birthplace of panel level die embedding technology and play a crucial role for enabling EMIB, the key technology to Intel’s data-centric business and heterogenous packaging. His team works with equipment, material, chemical and substrate suppliers to develop Si-fab backend-like technologies for panel level advanced packaging, and transfer technologies to Intel supplier factories to meet the demand of future Intel products.
International Semiconductor Industry Group (I.S.I.G.)
Company Profile
Established in 2010, the International Semiconductor Industry Group (ISIG) is a prestigious and trusted global platform, known for fostering collaboration and driving innovation across the semiconductor industry. With a strong foundation through its International Semiconductor Executive Summits (I.S.E.S.), ISIG orchestrates influential regional summits across the U.S., Middle East, Europe and Asia, fully endorsed by local governments and leading companies throughout the semiconductor supply chain.
At ISIG, we are more than just event organizers—we serve as a catalyst for shaping the future of the semiconductor industry. Through high-level executive recruitment, expert consultation, and strategic investor engagement, ISIG empowers global collaboration, helping industry leaders connect, collaborate, and innovate. Our vision is to create a trusted network that transcends borders and disciplines, uniting government officials, academic experts, and investors to tackle the most pressing challenges and seize the greatest opportunities in the semiconductor ecosystem.
Together, we ensure the semiconductor industry remains at the forefront of technological advancement and economic growth, shaping a sustainable future for the global market.
Panelist
Raja Swaminathan, Ph.D.
AMD
Dr. Raja Swaminathan is the Corporate Vice President of Packaging at AMD, spearheading the development of AMD’s advanced packaging and heterogeneous integration roadmap. With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan’s expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple’s Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators. Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to their name, Dr. Swaminathan was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology.
AMD
Company Profile
For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.
Panelist
Jim Li, Ph.D.
ASE
- Jim Li (Chung-Li) joined ASE in 1999 as a Sr. engineer for new package development. He served several roles as a manager for design team, modeling and measurement labs, and director for business promotion and Customer Engineering Integration.
- He is now Vice President for Fan-out, Power Module Development and Engineering System Management.
- Jim Li received Ph.D. from Chemical Engineering, Northwestern University, and holds more than 10 patents related to semiconductor packaging.
ASE
Company Profile
ASE is the leading global provider of semiconductor manufacturing services in assembly and test. With a proven track record spanning almost 40 years, ASE today is at the forefront of flexible, powerful, integration technologies that achieve criteria for improved power, performance, area, and cost requirements. Our comprehensive toolbox leveraging innovative technologies, such as die interconnection, wafer level fan out, embedded devices, conformal and compartmental shielding, integrated antenna, and others, are being refined and enhanced to support future generations of system integration. Heterogenous Integration through SiP is enabling significant innovation across dynamic application areas including AI, 5G, automotive, mobile, IoT and more. Our industry is driven by innovation, and through ASE’s miniaturization technologies, we are enabling transformative solutions that are literally changing lives, from health to transportation, from Robotics to AI, from IoT to 5G.
Website: ase.aseglobal.com
Panelist
Babak Sabi, Ph.D.
AWS Annapurna Labs
Dr. Babak Sabi is VP of Technology at AWS/Annapurna Lab. Babak joined AWS in 2024 after 40 years in Intel. Babak was Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development. During Babak’s tenure in ATTD 2.5D and 3D Advanced Packages were developed and ramp to high Volume Manufacturing. Additionally ATTD team made many advancement in Substrate and Test Technology.
Prior to leading ATTD, Babak oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices.
Babak joined Intel in 1984 after receiving Babak his Ph.D. in solid state electronics from Ohio State University in 1984.
AWS Annapurna Labs
Company Profile
Launched in 2006, Amazon Web Services (AWS) began exposing key infrastructure services to businesses in the form of web services — now widely known as cloud computing. The ultimate benefit of cloud computing, and AWS, is the ability to leverage a new business model and turn capital infrastructure expenses into variable costs. Businesses no longer need to plan and procure servers and other IT resources weeks or months in advance. Using AWS, businesses can take advantage of Amazon’s expertise and economies of scale to access resources when their business needs them, delivering results faster and at a lower cost.
Today, Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. With data center locations in the U.S., Europe, Singapore, and Japan, customers across all industries are taking advantage of our low cost, elastic, open and flexible, secure platform.
Panelist
Mike Rosa, Ph.D.
Onto Innovation
Mike Rosa is chief marketing officer (CMO) and senior vice president responsible for strategy at Onto Innovation. Prior to his current role, Mike served as CMO for Applied Materials ICAPS and Advanced Packaging Groups, where he was responsible for leadership of strategic and technical marketing, marketing communications, charting device segment inflection roadmaps and providing strategic business development support toward M&A activities. He has over 25 years’ experience in semiconductor engineering and technology, with roles that span device design and fabrication, equipment development, marketing and sales. His technical qualifications include B.Eng. (Hons) and Ph.D. degrees in Microelectronic Engineering and an MBA with dual majors in Marketing and Business Strategy. Mike has authored over 40 journal and conference publications and holds over 29 U.S. patents
Onto Innovation
Company Profile
Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.
General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com
Panelist
Jim Lin, Ph.D.
Powertech Technology Inc.
Dr. Jim Lin is Vice President of Advanced Technology & Wafer Level Package Operation. He is in charged of advanced packaging R&D, Business and Operation in PTI. Prior to BU head, Dr. Lin was AVP of Memory Packaging Research & Development. Dr. Lin joined PTI in 2006, led the development of memory packaging technology. Developed technologies including 8 to 32 chips memory stacking package, system integrated package of SSD, Package on Package(PoP), Heterogeneous multi-chip package(MCP), 3D TSV interconnection High Bandwidth Memory(HBM) and Fan-out Panel Level Package (FOPLP). Dr. Lin received his M.S. and Ph.D. degree both from National Tsing Hua University in Power Mechanical Engineering.
Powertech Technology Inc.
Company Profile
Powertech Technology Inc. (PTI), the world’s leading OSAT, was founded in 1997. We serve the international customers with services including chip bumping, chip probing, IC assembly, final testing, burn in, and system level assembly. In 2017 PTI expanded the production base to Japan to serve the local automotive electronics and IoT market. And in 2018, PTI began the construction of the newest Fan Out Panel Level Package manufacturing facility in Hsinchu Science Park.
PTI has over 18,000 employees world wide, and manufacturing facility located in Taiwan, China and Japan. PTI dedicates her efforts in developing advanced technologies, while carrying on as the world’s leading memory packaging and testing solution provider. Through strategic alliances and resource integration, PTI group relentlessly marches onward in the semiconductor packaging and testing field.
We drive our future growth with outstanding quality, cost, and delivery. Promise, Technology, and Integration represents our core values. With our ideaology, strategy, and core values, PTI stands as the world class OSAT.
Company Products & Services
PTI offers the services inculding Final test, Chip Probe, IC Packaging, Module Assembly, Quality Management. And provide wide range of technology solution for IC packaing including Panel Level Fan Out, TSV solution, Bumping, Flip chip, Antenna in Package.
-Panel Level Fan Out
Fan-out packaging is going to become the mainstream for high-end device application, especially for multi-die, heterogeneous integration for both active & passive devices. High density interconnect, excellent performance in electrical performance and power consumption can also be achieved by panel FO. PTI’ Panel level FO packaging offers the merits of high production efficiency with better utilization & unit output in comparison to wafer level FO.
Solution: CHIEFS® / CLIP® / PiFO® / BF2O®
TSV Solution-3DIC
3D IC is one kind of heterogeneous technology which is integrated vertically by Si wafers or chips. The interconnection is composed by u-bumps and Through Silicon Via (TSV). TSV fabrication is regarded as the heart of 3D IC because it provides the advantages of shortening the interconnection path, high function density, low power consumption, smaller form factor and high performance; these benefits make 3D IC get commercial success in some specific applications, such like HPC and AI.
TSV Solution-CMOS Image Sensor
CMOS Image Sensor (CIS) is an electronic device that converts an optical image into an analog signal. Recently, the most attractive is stack-CIS, that BSI CIS, memory wafer and Image Signal Processor(ISP) wafer are vertically integrated and higher performance, lower power consumption would be the advantages for high-end application.
Bumping
Wafer bumping is a metal bump that grows on a wafer, and each bump is an IC signal contact. Unlike conventional interconnection through wire-bond, bond pads are placed at peripheral area , IO pads for bumping could be distributed all over the surface of the chip, thus chip size could be shrunk and electrical path could be optimized.
