- 10:30 – 11:00
Advanced Packaging: Enabling Moore’s Law’s Next Frontier
Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.
Dr. Raja Swaminathan
Dr. Raja Swaminathan is CVP, Advanced Packaging instrumental in the development of AMD’s industry leading advanced packaging roadmap. Raja has been a leader in silicon-package-system architecture definition and a co-design expert with extensive experience introducing new technologies and innovation across the silicon-packaging spectrum at Intel, Apple and AMD. He’s helped enable PPAC (power, performance, area, and cost) improvements as well as introduction of novel heterogeneous architectures throughout his career: EMIB, Apple’s Mx package architectures, 3D V-Cache, Elevated Fan-Out Bridge, High Performance Fanout to name a few. Raja received his Bachelors’ from IIT Madras and PhD from Carnegie Mellon University and has over 40 US patents in the field. He is an IEEE Senior Member and is on the technical advisory board for the Semiconductor research corporation (SRC) and Deca Technologies.
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