Edge Artificial Intelligence (Edge AI) has emerged as a transformative paradigm, enabling real-time data processing and decision-making at the edge of networks, close to data sources. As the demand for high-bandwidth and energy-efficient edge computing grows, innovations across the hardware stack—from chip design to chiplet integration—are becoming critical. Traditional SoC designs are increasingly constrained by power, thermal, and scaling limits. In response, designers are adopting heterogeneous integration strategies, leveraging specialized processing units such as NPUs (Neural Processing Units), TPUs (Tensor Processing Units), and DSPs (Digital Signal Processors) optimized for AI workloads. Chiplets enable greater scalability, flexibility, and reuse, significantly reducing design complexity and time-to-market for edge AI solutions. Here we share chip design tailored for Edge AI, highlights the opportunities and challenges associated with chiplet-based architectures, and discusses future directions in design methodologies, and interconnect. ITRI has complete 12” process line for 3D/2.5D and fan-out process including a 2.5 µm fine-pitch Cu/oxide hybrid bonding structure, 12” wafer-to-wafer hybrid bonding at a low temperature of 200°C without thermal compression, and some use cases demonstrated for IIoT application