The Challenge of Speed – The Rapidus Model for a New Manufacturing Era
As the miniaturization of advanced logic processes continues, the time from design to commercialization is lengthening. This is due to the increasing difficulty of the manufacturing process, design, and verification associated with the growing complexity of device structures. However, LSIs, such as processors and accelerators for AI, are evolving at a rapid pace and must be commercialized in a short period of time to meet time- to-market requirements. We will introduce the Rapidus model, which solves this problem and achieves short TAT manufacturing.
Joined Toshiba, Semiconductor Device Engineering Labs. in 1988 and engaged in development of advanced SRAM/Logic technologies. 2006-2010: engaged in development of 32nm~20nm CMOS platform technologies with IBM as Toshiba’s representative (VP of R&D). 2013 Senior Manager of Advanced Memory Technology Development Dept. 2022 Director of Memory Technology R&D Center. Joined Rapidus Corporation in April 2023.