• 08:00 – 08:50


  • 09:00 – 09:15

Welcome Speech

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Salah Nasri

Senior Advisor to President


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International Semiconductor Executive Summits (ISES) holds a significant position within the semiconductor industry. Since 2010 we have scaled 8 major successful regional events globally. Our initiatives to date have been fully supported by local governments. For e.g., ISES USA is hosted in partnership with the Greater Phoenix Economic Council, ISES Taiwan is hosted in partnership with ITRI, ISES EU is hosted in partnership with the EU Commission, ISES Southeast Asia in partnership with Invest in Penang. We serve as a platform where senior executives in technology, manufacturing and R&D from various semiconductor companies, technology providers, and related industries gather to exchange information, shape strategies, and discuss the industry’s direction. Our summits have influenced industry trends and decisions due to the high-level discussions that take place.

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  • 09:20 – 09:40

Chiplets and Advanced Heterogeneous Integration

With the ever-increasing demand for computing performance for mobile, IoT, AI, Big Data and automotive applications, the need for new solutions is growing due to the slowdown of Moore’s Law and computing power solutions. Heterogeneous integration is one of the key platforms to enable higher bandwidth and density for HPC and AI systems. This presentation will discuss how chiplets and advanced heterogeneous integration are enabling next generation computing.

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Dr. Terry Wu


Samsung Electronics

Dr. Wu is currently working as Director of Business Development Team, AVP, Samsung Electronics. Prior to joining Samsung, he was CTO of Chengdu ESWIN System IC. He had also held several key positions in SJSemi and TSMC. Wu received DPhil in Inorganic Chemistry from Oxford University, and MS & BS degree in Chemical Engineering from National Taiwan University & National Chung Hsing University, respectively. Dr Wu was granted several awards in recognition of his contribution in Advanced Packaging, including 2018 Jiangshu Innovative & Entrepreneurial Talent Award, 2019 Wuxi Taihu Talent Award, 2021 Chengdu Golden Panda Talent Program, and 2022 CSTIC Best Young Engineer Award from SEMICON China. He has 14 journal and conference papers, with over 680 citations and H-index of 11. He also holds 40 US patents and 144 China patents on microelectronic packaging.

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Samsung Electronics Co., Ltd. engages in the manufacturing and selling of electronics and computer peripherals. The company operates through following business divisions: Consumer Electronics, Information Technology & Mobile Communications and Device Solutions. The Consumer Electronics business division provides cable television, monitor, printer, air-conditioners, refrigerators, washing machines and medical devices. The Information Technology & Mobile Communications business division offers handheld products, communication systems, computers and digital cameras. The Device Solutions business division comprises of memory, system large scale integrated circuit and foundry. The company was founded on January 13, 1969 and is headquartered in Suwon, South Korea.

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  • 09:45 – 10:05

Chiplets and System Integration – Key Concepts and Implementation

In this presentation, Jianmin Li, Director of R&D at Amkor Technology – China, discusses the key concepts and implementations of chiplets and system integration. Li highlights the strong trends in chiplets and heterogeneous integration products, which offer new ways to achieve innovative product architectures while maintaining optimal Performance/Power/Area/Cost (PPAC) ratios for the future of the industry. Li emphasizes the need for advanced IC packaging capabilities to support these approaches, and notes that OSATs and Foundries are actively responding to enable this integration.

The presentation emphasizes the importance of starting with a 2D module and augmenting it with 3D as necessary for enhanced performance and differentiation. Additionally, Li mentions Amkor’s involvement as a contributor member of the UCIe™ ecosystem, which aims to define next-generation computing standards. Overall, this presentation provides valuable insights into the evolving landscape of chiplets and system integration, positioning the speaker as a seasoned professional in the field.

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Jianmin Li photo

Jianmin Li

Packaging R&D Director, Amkor Technology China, Inc.

Amkor Technology, Inc.

Jianmin joined Amkor in 2013, and is currently packaging R&D director in Amkor Assembly & Test (Shanghai) Co. Ltd, responsible for developing various package type including memory SCSP, flip chip package, SiP and optical sensor packages. He has more than 20 years of experience in assembly process engineering area. Prior to joining Amkor, Jianmin was an assembly process engineer in Intel and IBM. He holds a Master degree in Material Engineering from Fudan University.

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As one of the world’s largest providers of high-quality semiconductor packaging and test services, Amkor has helped define and advance the technology landscape.

We deliver innovative solutions and believe in partnering with our customers to bring 5G, AI, Automotive, Communications, Computing, Consumer, IoT, Industrial and Networking products to market.

As a truly global supplier, Amkor has manufacturing and test capabilities as well as product development and support offices in Asia, Europe and the US.

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  • 10:05 – 10:45

Networking Break, Business Meeting

  • 10:50 – 11:10

Heterogeneous Integration Enabled by Advanced Chiplet Packaging

With the growing demand of high performance IC, heterogeneous system integration of multiple smaller chiplets by advanced packaging technology becomes one of the major driving forces of the semiconductor industry innovation. New technologies in high bandwidth 2.5D and 3D interconnection enable complex designs implementation. Chip-Package co-design is prerequisite to meet the target performance and STCO (system-technology co-optimization) methodology is critical to advance chiplet architecture for optimal system performance.

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Dr. Yang Cheng photo

Dr. Yang Cheng

Senior Director Design Service BU

JCET Group Co., Ltd.

Dr. Yang has 20 years’ of experience in electronics system and IC packaging development. At present he is senior director of advanced packaging and SiP design at JCET. Before joining JCET, he was at Flex on SiP products and technology development in IoT, automotive, medical, and industrial applications, covering design, manufacturing, and testing areas. He has worked at Intel on memory packaging design and technology development for 13 years. Dr. Yang hold a Ph.D. degree from National University of Singapore, EMBA from Washington University in St. Louis, and Master and Bachelor from Shanghai Jiaotong University.

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JCET Group is the world’s leading integrated-circuit manufacturing and technology services provider, offering a full range of turnkey services that include semiconductor package integration design and characterization, R&D, wafer probe, wafer bumping, package assembly, final test and drop shipment to vendors around the world.

Our comprehensive portfolio covers a wide spectrum of semiconductor applications such as mobile, communication, compute, consumer, automotive, and industrial, through advanced wafer-level packaging, 2.5D/3D, System-in-Package, and reliable flip chip and wire bonding technologies. JCET Group has two R&D centers in China and Korea, six manufacturing locations in China, Korea, and Singapore, and sales centers around the world, providing close technology collaboration and efficient supply-chain manufacturing to our global customers.

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  • 11:15 – 11:35

Interconnection Define Computing: Key Technology for Next Generation Computing Paradigm Evolution

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MoChen Tian photo

MoChen Tian

Founder and CEO


In 2021, he founded Kiwimoore and assumed the role of CEO. Kiwimoore is among the world’s pioneering companies, focusing on universal interconnect chiplets and system-level solutions. These are built on next-gen computing architecture and offer leading high-performance general-purpose chiplets and solutions. Their aim to enable high-computing power chips to achieve a significant leap in performance.

Former Global Vice President of NXP Semiconductors, he was accountable for marketing and team management in Greater China, encompassing Smart ID, MCU, Mobile, IoT, and other product lines.

He successfully spearheaded the product line definition in China, overseeing the entire process from market demand assessment to specification definition and product realization. This effort resulted in cumulative product lifecycle sales of $5 billion.

Previously, he served as the Head of Marketing Asia Pacific in the Chipcard & Security Division at Infineon Technologies.

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Founded in early 2021, Kiwimmore is among the world’s pioneering companies, offering “universal interconnect chiplets and system-level solutions” based on the Chiplet architecture,our primary product lineup comprises two types of products: High-speed interconnect IO Die
and High-performance interconnect Base Die. Additionally, we provide a series of Die2Die IPs, Chiplet software design platforms, and other hardware and software products.

We target the AIGC-driven high-performance computing markets, such as data centers, autonomous driving, personal computing platforms, and more. Our company is dedicated to delivering chiplet system-level solutions with the interconnect chiplets. These solutions are designed to assist our customers in expediting the development of intricate, high-computing-power chips in a more efficient manner.

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  • 11:40 – 12:00

The Opportunity & Challenge of OSAT for the Coming Chiplet Integration Package

The development of semiconductor IC follows Moore’s law. Today, it has encountered great challenges, whether it’s the physical size limit or the advanced manufacturing process with huge investment costs ,and so on have formed huge pressure on the industry. Packaging is considered to be the focus of continuing semiconductor chip integration in the next decade development direction, especially in the 2.5D, 3D packaging technology brought by the chiplet concept; We see that wafer factories have made faster progress in 2.5D and 3D packaging, What are their opportunities for OSAT? What challenges will it face?

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Yupeng Xu


Forehope Electronic (Ningbo) Co., Ltd.

Xu YuPeng, CTO of FOREHOPE electronic(NINGBO) Co.LTD since June of 2018. 21 years experience in semiconductor assembly house. Before FHEC, Mr Xu has 7 years experience work as VP of ICBU in JCET (2011~2018). and 7 years RND engineer/Manager in Statschippac shanghai(2004~2011). 2 years process engineer in ASE shanghai(2002~2003). Mr Xu experienced with all kinds of IC package assembly process & technology ,especially in SiP integration, Automotive IC , wafer level package development etc.

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Forehope(FHEC) was founded in Nov 2017, devoted to a worldwide and industry-leading high-end IC ,package assembly and testing . The end customer application covered consumer electronics,AI, industry, Automotive, Network,Data center etc. We can deliver package type include WBQFN, WBLGA, WBBGA, FCCSP, Hybrid-BGA, SiP, MEMS.,QFP, FCBGA etc. And also we can provide wafer level package include Bumping, WLCSP. Forehope continue to research & develop advanced wafer level package like as Fan-out, 2.5D/3D , which for chiplet solutions.

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  • 12:05 – 13:15

Networking Lunch

  • 13:20 – 13:40

Chiplet Process Integration Based on Glass Substrate and TGV Process

The hole size can be less than 15 microns, and the metal filling capacity aspect ratio can reach 10:1. It adopts high-density intermediate layer wiring, with a minimum line width and line spacing of less than 1.5um, meeting the needs of high-density interconnections such as high-performance memory and CPU. The entire packaging body uses glass as the core layer of the intermediate layer, and uses the “RDL-First” process to flip the chip onto multiple layers of RDL wiring layers to achieve electrical interconnection. Compared with TSV, it reduces parasitic capacitance and inductance effects, reduces transmission signal delay, and can be widely used in high-frequency transmission fields.

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Dr. Wenbiao Ruan photo

Dr. Wenbiao Ruan

R&D Director

Xiamen Sky Semiconductor Technology Co., Ltd.

Ph.D, majoring in Electronics and Solid State Electronics at the Chinese Academy of Sciences, currently serving as the Director of R&D at Xiamen Yuntian Semiconductor Technology Co., Ltd., responsible for the research and development of processes such as through glass via (TGV), fanout packaging (WL-FO), wafer level packaging technology, and glass based high-frequency devices. He has successively served in SMIC., Institute of Microelectronics and Detection Technology. In 2010, he was appointed as an associate researcher at the Institute of Microelectronics, conducting research on the modeling of integrated circuit manufacturing processes and manufacturability design methodology for 65 nm and below node, and participating in and completing multiple national major special research projects. Published over 10 articles and applied for 18 patents.

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Founded in July 2018, Xiamen Sky-semi commits to the development and industrialization of advanced packaging and system integration technology for high-speed and high-frequency communication applications. Through independent R&D and collaborative innovation, we provide customers with integrated solutions and services from collaborative product design, process research and development to mass production.

The main business of Xiamen Sky-semi includes Wafer Level 3D Package (WLP), Fan Out Package (FO), System in Package (SIP) and Module, IPD device manufacturing, High Density Glass Through Via (TGV) technology, manufacturing of high precision antenna ,etc. We have provided design, packaging and integration services for nearly 100 customers at home and abroad。Sky-semi has a core team with outstanding innovation ability that has broken through a series of core and key technologies and has full range of wafer level system packaging as well as precision manufacturing capabilities from 4 inch, 6 inch, 8 inch to 12 inch.

Sky-semi Semiconductor based on technological innovation embarking on seize the historical opportunity to achieve leapfrog development in the new era of global semiconductor industry competition pattern by adhere to customer-centered ,Innovative and progressing philosophy,5G application as a breakthrough.

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  • 13:45 – 14:05

Memory and Processors for Chiplet Designs

Recent application of AI drives strong demand for HPC chip, and in the latest technology, 2.5D& 3D package solution provides the best electrical performance for these type chips; In this presentation, speech will focus on the CHIPLET design challenge which focus on the HBM& Logic chip multi connection.

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Simon Zhang photo

Simon Zhang


Jiangsu Silicon Integrity Semiconductor Technology Co., Ltd.

VP of JSSI with 20+ years R&D and PM experience in advanced package area, full global OSAT operation experience. He holds more than 25+ patents in 2.5D PKG area and worked in global enterprise like SPIL, TI.

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JSSI, registered in Sep’2020 in Nanjing,Jiangsu Province, P.R.C, and factory located in the same industry park with TSMC-12inch Nanjing Plant. JSSI business focus on Semiconductor Assembly & Test service including Bumping/WLCSP/eWLB/WB-FCQFN/LGA/BGA/2.5D package solution. JSSI core management and R & D team worked in advanced package area more than 20 years, and company committed to provide first-class technology services for customers; JSSI factory has 1700+ employees and obtained ISO9001, QC080000, ISO14001, ISO27001,TS16949 and other system certifications. JSSI R&D team worked with several key GPU/CPU design house to focus on the 2.5D PKG design and test vehicle sample manufacturing now.

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Equipment and Material Supplier

  • 14:10 – 14:30

Advanced Packaging Materials and Evaluation Platform at Resonac

An increased density of IC chips and other components to increase processing speed highly will be required for post-5G/6G systems. Therefore, there is a need for technologies that allow for high-density packaging of differing chips within a single semiconductor package.

Resonac has started Packaging Solution Center to propose one-stop solution for customers in 2019 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package.

We are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large advanced package.

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Hidenori Abe

Electronics R&D Center GM

Resonac Corporation

Mr. Abe is leading R&D of semiconductor materials in general and promoting co-creation activities at Resonac, which is an integrated company of Showa Denko K.K. and Showa Denko Materials Co., Ltd., (formerly Hitachi Chemical Co., Ltd.), After serving as a General manager of CMP slurry business sector and a corporate marketing manager at Hitachi Chemical.

He was involved in the launch of the Packaging Solution Center, which is open innovation hub in advanced packaging development.

He had been engaged in the development of semiconductor molding compounds since 1998.

He holds an Executive MBA from Oxford, UK.

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On January 1, 2023, Showa Denko K.K. and Showa Denko Materials Co., Ltd. merged and transformed themselves into newly integrated company “Resonac”. Resonac defines its purpose as “Change society through the power of chemistry.” Resonac aims to be a world-class functional chemical manufacturer, creating functions necessary for the times, supporting technological innovation, and contributing to the sustainable development of our customers. Resonac is Global No.1 semiconductor materials supplier (except for Si wafer). In order to achieve technological innovation for solving various social issues, it is essential for us to make wide-ranging co-creative efforts with partners, and Resonac is open to collaboration including 1on1 co-development with any partner.

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  • 14:35 – 14:40

Deep Reactive Ion Etch – Enabling Advanced Specialty Technologies and Packaging Applications

A wide range of applications in consumer electronics, automotive electronics, IoT applications and 5G cellular communications are increasingly dependent on devices such as sensors, including MEMS, and CMOS image sensors, RF Devices, advanced power semiconductors and Bipolar-CMOS-DMOS ICs. This trend means these specialty technologies currently account for approximately 30% of all global IC demand1.

Deep reactive ion etching (DRIE), initially developed for the fabrication of MEMS devices2, has since become one of the key enabling technologies used in the fabrication of such devices as well as in advanced packaging schemes that require through silicon via (TSV) integration. At the same time, demands on the capability of the DRIE process have increased as device architectures have advanced and production has shifted to high volume manufacturing on 300mm substrates.

Lam Research’s Rapidly Alternating Process (RAP) and Syndion® DRIE tools have been well established in such high-volume manufacturing for more than two decades. Today we are focused on continued enhancement of our systems and process control methodologies in order to meet future requirements.

In this work we show how development of our deep silicon etch hardware and process capabilities is resulting in significant improvements in on-wafer results and supporting next generation device fabrication. Such challenges include the continuous improvement of process productivity, improved profile control, achieving smoother etched sidewalls, and improving uniformity of both etch depth and feature CD.

To illustrate this, we will discuss critical applications such as advanced deep trench isolation (DTI) in CMOS image sensors, etching of power device trenches and TSV fabrication.

1. IC Insights, McClean Report, Feb 2022

2. Franz Laermer and Andrea Schilp, Robert Bosch GmbH, Method of anisotropically etching silicon, United States Patent 5501893

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Dr. David Haynes

VP Strategic Marketing

Lam Research Corporation

David gained a B.Eng and PhD in Materials Engineering from Swansea University. His PhD thesis was in the field of organic semiconductors for electronic and optoelectronic applications.

In his professional career, David has accrued more than 25 years of experience in the Semiconductor Capital Equipment and research instrumentation sectors. Focused on new technology development, he has a strong process background in plasma etch and deposition for optoelectronics, photonics, MEMS, Power and RF Electronics, as well as advanced chip packaging technologies.

Building on this technical knowledge, David has a proven track record in developing strategic business partnerships, specializing in new technology developments and introduction of enabling process capabilities to leading semiconductor fabs worldwide.

David Joined Lam Research in June 2016. He is currently Vice President of Strategic Marketing in Lam’s Customer Support Business Group and is responsible for Lam’s strategy in Specialty Technologies.

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Lam Research Corporation is a trusted global supplier of innovative wafer fabrication equipment and services to the semiconductor industry. Our strong values-based culture fuels our progress, and it’s through collaboration, precision, and delivery that we are driving semiconductor breakthroughs that define the next generation. Lam Research (Nasdaq: LRCX) is a FORTUNE 500® company headquartered in Fremont, California, with operations around the globe. Learn more at www.lamresearch.com

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  • 14:45 – 14:50

Tailored Solutions for the Semiconductor Industry Powered by TRUMPF

With short introduction of TRUMPF and short video show how we active in Semiconductor industry, Mr. Czaja will Define our tailored solutions for customers in the semiconductor industry around the world.

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Dariusz Czaja

Managing Director of TRUMPF Hüttinger Asia / General Manager of TRUMPF Hüttinger China

TRUMPF Huettinger Electronics (Taicang) Co., Ltd.

Dariusz Czaja joined TRUMPF Huettinger in 2007, used to work in Poland and Germany. He holds the General Manager position at TRUMPF Huettinger China since 2017. Dariusz Czaja has over ten years working experience in the market management in various industry segments such as Solar, Display, Glass as well as Semiconductor. He studied Electrical Engineering at the Radom University of Technology.

Since from July 2022 until now Dariusz Czaja as Managing Director at TRUMPF Huettinger Asia.

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TRUMPF Hüttinger, headquartered in Germany, is the global market leader for process power, semiconductor, display, and solar supplies.

We are developing, manufacturing plasma power supplies for a wide range of deposition and dry-etch processes. Our products offer best in class uptime, energy efficiency, coating quality and high productivity. TRUMPF Hüttinger has sales and service subsidiaries in Asia, Europe and America.

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  • 14:55 – 15:00

Pushing the Boundaries of Thermal Management to Address Challenges in Wafer Test and Advanced Packaging

In today’s rapidly evolving technology landscape, the semiconductor industry is constantly pushing the boundaries of innovation to meet the demands of increasingly complex systems. With the popularity of Artificial Intelligence and high demand for new power management, the importance of thermal management cannot be overstated.

As semiconductor devices shrink in size and complexity increases, they generate higher power densities, resulting in elevated operating temperatures. This poses critical wafer testing challenges for manufacturers in terms of temperature accuracy and uniformity, as even minor thermal deviations can significantly impact the performance and reliability of these advanced chips.

This presentation will introduce ERS’s latest developments in wafer probing and advanced packaging; two critical areas that are geared towards maximizing yield and guaranteeing performance.

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Laurent Giai-Miniet


ERS Electronic GmbH

Laurent is the CEO of ERS electronic GmbH, and oversees the Sales, Marketing, Applications and Business Development team. He has more than 25 years of experience in the semiconductor industry and has held leadership positions in renowned companies such as Texas Instruments and Infineon, as well as in high-tech start-ups. Laurent has an MBA from the Institut d’Administration des Entreprises of Aix-en-Provence (France).

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ERS electronic GmbH, located near Munich, has been providing innovative thermal management solutions to the semiconductor industry for more than 50 years. The company has gained an outstanding reputation, notably with its fast and accurate air cooling-based thermal chuck systems for test temperatures ranging from -65 °C to +550 °C for analytical, parameter-related and manufacturing probing. In 2008, ERS extended its expertise to the Advanced Packaging market. Today, their fully automatic and manual debonding and warpage adjust systems can be found on the production floors of most semiconductor manufacturers and OSATs worldwide. The company has received widespread recognition in the industry for their ability to tackle complex warpage issues that arise in the Fan-out wafer-level packaging manufacturing process. ERS’s headquarter, sales department, engineering center and production facilities are in Germany, and they also have sales and support offices worldwide.

Phone: +49 898941320
Email: info@ers-gmbh.de
Website: www.ers-gmbh.com

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  • 15:05 – 15:45

Networking Break, Business Meeting 

  • 15:50 – 16:35

Focusing on the Collaboration and Leverage between UCIe and China Chiplet Standards

Prof. Qinfen Hao photo

Prof. Qinfen Hao


Institute of Computing Technology, Chinese Academy of Science

Dr. Qinfen Hao, graduated from the Institute of Computing Technology, Chinese Academy of Sciences (ICT) in 2001 with a Ph.D. in System Architecture. He is currently the director of the Interconnect Technology Laboratory of ICT, a professor at the University of Chinese Academy of Sciences, the secretary-general of the China Computer Interconnect Technology Alliance (CCITA) and the director of the Wuxi Institute of Integrated Circuit Interconnect Technology.

He has successively engaged in the design and research of high-performance computer, high-end SMP server, several important chips in computer such as cache coherence interconnect chip, CPU, etc. He has won the second prize of the Chinese National Science and Technology Progress Award twice, in charge of over three national scientific research projects, served as the chief scientist of the Ministry of Science and Technology’s key research and development program. He published more than 40 scientific papers and applied for more than 30 patents until now.

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Haopeng Liu

Technical Solution VP

AkroStar Technology Co., Ltd.

Haopeng Liu has nearly 20 years of experience in IP product development and management, who has accumulated rich technical experience from IP products to systems. Besides, he has mastered the latest technology and application trends in the IP industry and ecosystem. Mr. Liu, served as IP Technical Support Manager and Senior Solutions Manager in Synopsys China, joined Synopsys China as the first IP engineer in 2007. He is always committed to developing and supporting many local design and manufacturing enterprises. He also won many honors such as Synopsys Global Outstanding Employees. He once served in Hisilicon, mainly responsible for IP design and implementation.

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AkroStar was founded in June 2020 and is a leading Chinese enterprise specializing in advanced interface IP. We are committed to the research and development of domestically produced advanced interface IP and breaking through “bottleneck” technologies. AkroStar offers comprehensive high-speed interface IP solutions, including PCIe, Serdes, DDR, D2D, USB, MIPI, HDMI, SATA, SD/eMMC, etc., covering a full-stack complete IP solution compliant with the latest protocol standards.

Company website:https://www.akrostar-tech.com/

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Dr. Fengze Hou

Associate Professor

Institute of Microelectronics of the Chinese Academy of Sciences

Fengze Hou is an IEEE senior member. He received his Ph.D. from the Delft University of Technology, Delft, The Netherlands, in 2020. In 2012, he joined the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), in Beijing, China. From 2013 to 2021, he was a senior engineer at the National Center for Advanced Packaging (NCAP), Wuxi, China. Dr Hou is an associate professor at the IMECAS. He has authored or coauthored over 60 articles in journals and international conferences and holds more than 20 patents. He first proposed the PCB-embedded SiC MOSFET packaging technology in the world. His interests cover chiplet and heterogeneous integration, advanced packaging, chip power delivery, thermal management, and thermo-mechanical reliability.

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The Institute of Microelectronics (IME) of the Chinese Academy of Sciences (CAS) was established in 1958 as the CAS No. 109 Semiconductor Factory under the former CAS Institute of Applied Physics. Its original goal was to meet the nation’s strategic need to develop a high-frequency transistor computer. After numerous changes and mergers, it assumed its current name in 2003.
The IME is the only comprehensive scientific research institution in China, capable of carrying out full-chain research and development from microelectronic principal devices, integration processes, high-end chips, advanced packaging, and manufacturing equipment to applications.
IME comprises a national key laboratory, two CAS key laboratories, 11 research departments, and three technology research centers, covering all the main research areas of microelectronics. IME has a Ph.D. program in electronics and information; two master’s degree programs in IC engineering, and electronic and communication engineering, respectively; and a postdoctoral program in microelectronics.
IME has established long-term cooperative relationships with many national research institutions, universities, and companies in such countries as the United States, the United Kingdom, Germany, Japan, and Singapore, etc. A large number of delegations visit the institute every year, giving lectures, conducting academic exchange, and undertaking cooperative research projects.

Company website: www.ime.ac.cn

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Kaisheng Ma

Chief Scientist

Polar Bear Tech

Kaisheng Ma is now an Assistant Professor in Institute for Interdisciplinary Information Sciences (IIIS), Tsinghua University. Founder of Polar Bear Tech. He received his Ph.D. in Computer Science and Engineering at the Pennsylvania State University. His research focuses on Robust and Efficient AI Algorithms, Post-Moore Architecture, and High-Performance Chips, especially the advanced chip architecture in the post Moore era and the corresponding design methodology and tool chain. Dr. Ma has published papers on top conferences including NeurIPS, ICCV, AAAI, CVPR, ISCA, ASPLOS, MICRO, HPCA, DAC etc. He has won many awards and honors, including: 2015 HPCA Best Paper Award, 2016 IEEE MICRO Top Picks, 2016 Penn State CSE Department Best Graduate Research Award, 2017 ASP-DAC Best Paper Award, 2018 EDAA Best Dissertation Award, and Springer Nature Research Highlights from China Collection Award 2020.

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Polar Bear Tech(Xi’an) Co.,Ltd. founded from the Institute for Interdisciplinary Information Sciences of Tsinghua University, incubated by Xi‘an Institute for Interdisciplinary Information Core Technology, registered and established on July 9, 2021 and officially settled in the Software New Town in November 2021. Kaisheng Ma, an Assistant Professor of the Institute for Interdisciplinary Information Sciences of Tsinghua University, served as the Chief Scientist.

This company is committed to reducing the design period and NRE cost of large-scale and high-performance chips through Chiplet technology, and quickly realizing the iterative upgrading and function addition of products, and aims to provide customers with low-cost and flexible solutions from algorithms to server clusters.

Company website: https://www.bjxxtech.net/

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Market Research

  • 16:40 – 17:00

Memory and Processors for Chiplet Designs

The rise of generative AI applications and high-performance computing (HPC) in data centers has boosted demand for high-speed memory and computing devices with low-latency interfaces. In this context, heterogeneous integration and chiplet architectures enabled by advanced packaging approaches (e.g., hybrid bonding) are being regarded as the most promising solutions to address the memory-bandwidth bottleneck and increase the performance of computing systems via a tight integration of logic and memory functions.

This talk will provide an overview on the interplay between memory and processors in terms of technology and markets trends, describing the main solutions, the challenges, and the opportunities ahead for semiconductor players.

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Simone Bertolazzi, PhD.

Principal Technology & Market Analyst

Yole Intelligence

Simone Bertolazzi, PhD, is a Principal Technology & Market Analyst at Yole Intelligence (part of Yole Group), working with the Semiconductor, Memory, and Computing division. He is a member of Yole’s Memory team and contributes daily to the analysis of memory markets and technologies, their related materials, and fabrication processes. Simone obtained a PhD in Physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), where he developed flash memory cells based on heterostructures of 2D materials and high-κ dielectrics. Simone also earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.

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Yole Group is an international company recognized for its expertise in the analysis of markets, technological developments, and supply chains, as well as the strategy of key players in the semiconductor, photonics, and electronics sectors.

With Yole Intelligence, Yole SystemPlus and Piséo, the group publishes market, technology, performance, reverse engineering and costing analyses and provides consulting services in strategic marketing and technology analysis. The Yole Group Finance division also offers due diligence assistance and supports companies with mergers and acquisitions.

Yole Group benefits from an international sales network. The company now employs more than 180+ people.

More information on www.yolegroup.com.

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  • 17:05 – 17:10

Closing Remarks

  • 17:15 – 18:25

Networking Reception

  • 18:30 – 20:30

Gala Dinner and Appreciation Award Ceremony

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