• 07:50 – 08:30

Registration

  • 08:35 – 08:55

ISES Welcome Address

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Kamel Ait Mahiout photo

Kamel Ait Mahiout

President

ISES

Kamel Ait Mahiout is a seasoned professional with over 30 years of experience in the electronics industry. His expertise spans from RF and Microwave engineering to executive roles in prominent companies such as Unity SC and Amkor Technology, where he significantly contributed to the growth and alignment of the businesses with key industry players.

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International Semiconductor Executive Summits (ISES) holds a significant position within the semiconductor industry. Since 2010 we have scaled 8 major successful regional events globally. Our initiatives to date have been fully supported by local governments. For e.g., ISES USA is hosted in partnership with the Greater Phoenix Economic Council, ISES Taiwan is hosted in partnership with ITRI, ISES EU is hosted in partnership with the EU Commission, ISES Southeast Asia in partnership with Invest in Penang. We serve as a platform where senior executives in technology, manufacturing and R&D from various semiconductor companies, technology providers, and related industries gather to exchange information, shape strategies, and discuss the industry’s direction. Our summits have influenced industry trends and decisions due to the high-level discussions that take place.

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Chiplet Ecosystem Acceleration: Strategy, Roadmap & Standardization

  • 09:00 – 09:30

Keynote

Chiplet Ecosystem Acceleration

The speaker will share the work of TSMC in Chiplet Ecosystem acceleration by following outlines.

Outlines:

  • Forces Driving Chiplet and Integration
  • Advanced CMOS Technologies
  • Advanced Packaging Technologies
  • Design Enablement and Ecosystem
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KC Hsu photo

K.C. Hsu

VP, Research & Development / Integrated Interconnect & Packaging

TSMC

Mr. K.C. Hsu is Vice President of Integrated Interconnect & Packaging at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), responsible for the development of TSMC’s system integration technologies, including 3D IC and advanced packaging. He possesses more than 30 years’ experience in the semiconductor industry.

Mr. K.C. Hsu received his B.S. in Physics from National Taiwan University and his M.S. in Technology Management from National Chiao Tung University.

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TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 281 distinct process technologies and manufactured 11,617 products for 510 customers in 2020 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 3-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan.

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  • 09:30 – 10:00

Keynote

HBM (High Bandwidth Memory) and Advanced Packaging Technology for AI Era

The semiconductor packaging industry is expected to grow in the coming years, driven by the increasing demands for semiconductor chips in various applications, such as smartphones, autonomous vehicles, 5/6G, high-performance computing, IoT devices, and artificial intelligence. Another trend is the increasing adoption of heterogeneous integration, where different types of chips, such as CPUs, GPUs, and memory, are integrated into a single package to improve performance and reduce power consumption.

To overcome the limitations of performance/power/density/bandwidth of cutting edge systems, and to create new business opportunity and new values, the importance of advanced packaging technologies is more increased. For the above reasons, the future of the semiconductor packaging industry looks promising, with the increasing demand for semiconductor chips in various applications and the emergence of new packaging technologies driving growth and innovation in the semiconductor industry.

Major semiconductor players accelerate the competition to lead semiconductor industry hegemony by the evolution of advanced packaging technology such as chiplets and 2.5D/3D heterogeneous integration.

SK hynix drive the innovation of packaging technology to meet the demand for higher bandwidth and capacity of memory devices requiring in the increased AI workload applications such as the advent of ChatGPT, an artificial intelligence chatbot. High bandwidth memory (HBM), offers the largest capacity and bandwidth and also comes with the most improved power efficiency enabled by an advanced packaging technology of novel 3D chip stacking. SK Hynix is taking the lead in the HBM market. It developed the world’s first HBM in cooperation with AMD in 2013 and continuously released second/third/fourth-generation HBMs (HBM2/HBM2E/HBM3), and has secured a market share of 60-70 percent. The chip-let technology based on heterogeneous integration will be another key driver for memory-centric systems various combination of logic and memory devices. By the evolution of advanced packaging technologies, SK Hynix will continuously lead the competitiveness of memory business and prepare the business innovation for beyond memory era.

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Kangwook Lee photo

Dr. Kangwook Lee

SVP and Head of PKG Development

SK Hynix

Dr. Lee has been one of critical leaders who are leading the era of 3D TSV stack memory such as HBM (High Bandwidth Memory) in semiconductor industry.

He has contributed broadly to, and led teams in, 3D integration/packaging R&D including core technology/product development/reliability study and mass production for HBM over 27 years.

Dr. Lee received the Ph.D. degree in machine intelligence and systems engineering from Tohoku University, Japan, in 2000. During his doctoral research at Tohoku University,

Dr. Lee proposed a new 3D-IC integration technology to achieve 3D devices with high performance and multi-functionality, leading this field in the world.

From 2001 to 2002, he was a Postdoctoral Researcher with the Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA.

He worked with Memory Division, Samsung Electronics Ltd., Korea, as a Principal Engineer from 2002 to 2008.

From 2008 to 2016, he worked with the New Industry Creation Hatchery Center (NICHe), Tohoku University, Japan, as a Professor.

From 2017 to 2018, he worked with R&D center, Amkor Technology Korea, as a VP.

He joined SK hynix 2018 and currently Senior VP, Head of PKG Development at SK Hynix, Korea.

Dr. Lee has led many interdisciplinary R&D programs on 3D integration, including integration of various materials and devices to achieve 3D devices/systems with high performance and new functionality,

3D-IC reliability research to investigate the impacts of 3D integration on the device performance and reliability, unique hybrid integration of nano-materials with Si, and product development of 3D stack DRAM

such as high-bandwidth memory (HBM). For over 27 years at universities and industries in Japan, US, and Korea, Dr. Lee has made exceptional technical contributions to and lasting impacts on 3D integration technology

and 3D product development in broad fields, such as material science, materials characterization/analysis, semiconductor device/process, electrical packaging, and Si micro-machining.

Dr. Lee has authored more than 230 scientific publications (peered journals, international conferences), co-edited 4 books, and given 43 tutorial/invited/keynote talks in international conferences including

IEEE IEDM, IEEE IRPS, VLSI Symposium, plus 23 US patent publications.

He has served as a frequent reviewer for a number of journals, including IEEE EDL, IEEE T- ED, IEEE CPMT, and technical program committees of international conferences, including IEEE ECTC, IEEE IRPS, IEEE EDTM, IEEE 3D SIC.

He is a Senior Member of IEEE.

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  • 10:05 – 11:05

Networking and Coffee Break Business Meeting Slot 1&2

  • 11:10 – 11:30

Powering the AI Revolution through Innovations in High Bandwidth Memory

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Bret Street

Bret Street

Senior Director of Advanced Packaging

Micron Technology, Inc.

Bret Street has over three decades of semiconductor packaging experience. He currently holds over 165 issued U.S. patents. He currently serves as Senior Director of Advanced Packaging Technology Development at Micron Technology Inc. in Taiwan. His team focuses on advanced packaging solutions to enable current and future Micron products like Micron’s industry-leading HBM3e and future HBM/Heterogeneous-enabled products. Over his career, Bret has served in technical leadership roles across Assembly, Test, Probe, Product Engineering, and Advanced Package Technology Development. His packaging solutions span Flip Chip, Imager, 3D TSV, Logic/Memory (HMC), High Bandwidth HBM2e, and HBM3e products. Bret has developed a broad skill set enabling products from the design, development, manufacturing, and mass production stages.

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Micron is a world leader in innovative memory solutions that transform how the world uses information. For over 40 years, our company has been instrumental to the world’s most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications.

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  • 11:30 – 11:50

Generative AI Driven Advanced Packaging and Materials Innovation

We have seen a tremendous explosion of computational growth for generative AI. The wide range of use cases is driving innovation to grow and expand AI model complexity. This expansion is driving a continued need to innovate the computational capabilities of the generative AI processors. More compute requires more memory, more performance and more SERDES data rates. All of this requires immense power to run. New advanced packaging technology, process technology and materials are needed to ensure we have the hardware to drive the AI revolution.

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Dr. Bill En photo

Dr. Bill En

CVP, Foundry Technology and Operations

AMD

26 years of experience in the Semiconductor Industry ranging from silicon wafer R&D, process technology, circuit design and foundry technology with over 65 patents and 30 publications. He graduated from Univ. of California Berkeley with a Ph.D in Electrical Engineering and Computer Sciences in 1996. He is currently Corporate Vice President at Advanced Micro Devices overseeing Foundry technology from initial R&D through production for all AMD products.

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For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.

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Glass Substrates Manufacturing

  • 11:50 – 12:20

Keynote

Advanced Packaging Technologies for Heterogenous Integration: Glass Core Package Substrate

(Virtual Presentation)

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Rahul Manepalli, Ph.D. photo

Rahul Manepalli, Ph.D.

Intel Fellow; Director Substrate TD Module Engineering

Intel Corporation

Rahul Manepalli is an Intel Fellow and Sr. Director of Module Engineering in the Substrate Package Technology Development Organization in Intel. Rahul and his team are responsible for developing next generation of materials, processes and equipment for Intel’s package pathfinding and development efforts. His team has been the driving force behind many of the technology innovations in Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and other substrate technologies. Rahul has also had an instrumental role in leading Intel’s assembly materials development and pathfinding efforts leading to several innovations in encapsulants, thermal interface materials and solder alloys. Rahul is the author of over 100 patent publications in semiconductor packaging, over 50 technical papers and invited talks and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.

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Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.

To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

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  • 12:25 – 13:40

Buffet Lunch

  • 13:45 – 14:35

Panel Session: Standardization for Chiplet and Advanced Packaging

Moderator
Dr. Kuan-Neng Chen photo

Dr. Kuan-Neng Chen

Chair Professor

NYCU

Dr. Kuan-Neng Chen is Chair Professor of Institute of Electronics in National Yang Ming Chiao Tung University (NYCU) in Taiwan. He received his Ph.D. degree in Electrical Engineering and Computer Science, and M.S. degree in Materials Science and Engineering, both from Massachusetts Institute of Technology (MIT). He was Vice President for International Affairs and Associate Dean of International College of Semiconductor Technology in NYCU, Program Director of Micro-Electronics Program in National Science and Technology Council in Taiwan, and a Research Staff Member at IBM Thomas J. Watson Research Center. 

Dr. Chen is the recipient of IEEE EPS Exceptional Technical Achievement Award, IMAPS William D. Ashmon – John A. Wagnon Technical Achievement Award, National Industrial Innovation Award, MOST Outstanding Research Award (2 times), MOST Futuristic Breakthrough Technology Award, NSTC Futuristic Breakthrough Technology Award, NCTU Distinguished Faculty Awards, NYCU/NCTU Outstanding Industry-Academia Cooperation Achievement Awards (7 times), Pan Wen Yuan Foundation Outstanding Research Award, CIE Outstanding Professor Award, CIEE Outstanding Professor Award, and IBM Invention Achievement Awards (5 times). He has authored more than 300 publications, including 3 books and 67 book chapters, and holds 87 patents. He was Guest Editor of MRS Bulletin and IEEE Transactions on Components, Packaging, and Manufacturing Technology. He served as General Chair of IEEE IITC and Program Co-Chair of IEEE IPFA, and committee member of IEDM, IEEE 3DIC, IEEE SSDM, IEEE VLSI-TSA, and IMAPS 3D Packaging. Dr. Chen is a Fellow of National Academy of Inventors (NAI), IEEE, IET, and IMAPS, and a member of Phi Tau Phi Scholastic Honor Society. 

In addition to his faculty position, Dr. Chen is Specially Appointed Professor of Tokyo Institute of Technology (Tokyo Tech) and Adjunct R&D Director in Industrial Technology and Research Institute (ITRI). Dr. Chen’s current research interests are three-dimensional integrated circuits (3D IC), advanced packaging, and heterogeneous integration. 

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NYCU was founded on the idea that, in a great university, people work across the disciplines to solve real-world problems. At our university, putting this idea into practice requires integrating Chiao Tung’s strengths in information and communications technology with Yang Ming’s strengths in biomedical research. It also requires contributing to fields located at the intersection of these research areas, for example, digital medicine and bioinformatics. And it requires training our students in such a way that the next generation will not be as constrained by disciplinary boundaries as the previous one.

At NYCU, we are striving to be a great university that transcends disciplinary divides to solve the increasingly complex problems that the world faces. We will continue to be guided by the idea that we can achieve something much greater together than we can individually. After all, that was the idea that led to the creation of our university in the first place.

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Panelist
Dr. Bill En photo

Dr. Bill En

CVP, Foundry Technology and Operations

AMD

26 years of experience in the Semiconductor Industry ranging from silicon wafer R&D, process technology, circuit design and foundry technology with over 65 patents and 30 publications. He graduated from Univ. of California Berkeley with a Ph.D in Electrical Engineering and Computer Sciences in 1996. He is currently Corporate Vice President at Advanced Micro Devices overseeing Foundry technology from initial R&D through production for all AMD products.

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For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.

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Panelist
Walter Chen photo

Walter Chen

SVP Greater China Sales & Marketing

Amkor Technology, Inc.

Walter joined Amkor in 2020 and is currently Sr. Vice President responsible for Sales & Marketing in Greater China. Prior to joining Amkor, Walter worked for Cree, Inc 17 years as a position for VP of LED Chips Marketing WW & LED Component Marketing in Asia. Also as a Board member of Lextar representative for Cree. Prior to Cree, he had 6 years of IC design house experience. He has 29 years of Semiconductor industry experience in total, focused on Sales & Marketing field. He holds a Master degree of Engineering Business Management from University of Warwick in UK.

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As one of the world’s largest providers of high-quality semiconductor packaging and test services, Amkor has helped define and advance the technology landscape.

We deliver innovative solutions and believe in partnering with our customers to bring 5G, AI, Automotive, Communications, Computing, Consumer, IoT, Industrial and Networking products to market.

As a truly global supplier, Amkor has manufacturing and test capabilities as well as product development and support offices in Asia, Europe and the US.

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Panelist
Bret Street

Bret Street

Senior Director of Advanced Packaging

Micron Technology, Inc.

Bret Street has over three decades of semiconductor packaging experience. He currently holds over 165 issued U.S. patents. He currently serves as Senior Director of Advanced Packaging Technology Development at Micron Technology Inc. in Taiwan. His team focuses on advanced packaging solutions to enable current and future Micron products like Micron’s industry-leading HBM3e and future HBM/Heterogeneous-enabled products. Over his career, Bret has served in technical leadership roles across Assembly, Test, Probe, Product Engineering, and Advanced Package Technology Development. His packaging solutions span Flip Chip, Imager, 3D TSV, Logic/Memory (HMC), High Bandwidth HBM2e, and HBM3e products. Bret has developed a broad skill set enabling products from the design, development, manufacturing, and mass production stages.

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Micron is a world leader in innovative memory solutions that transform how the world uses information. For over 40 years, our company has been instrumental to the world’s most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications.

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Panelist
Kam Lee photo

Kam Lee

Deputy Head of TSMC Advanced Packaging Technology and Service

TSMC

Kam is currently the Deputy Head of TSMC Advanced Packaging Technology and Service. He joined TSMC earlier last year in March 2022 from Intel, where he served for 27 years in various roles in technology development, product development and high-volume manufacturing. Previously, he held the role as the Vice President and General Manager in Intel’s product engineering development group. At TSMC, Kam is actively working with his colleagues to advance the TSMC advanced packaging and testing technologies to serve its foundry customers.

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TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 281 distinct process technologies and manufactured 11,617 products for 510 customers in 2020 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 3-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan.

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Silicon-Photonics and Co-Packaged Optics Session

  • 14:40 – 15:00

Heterogeneous Integration for Photonic Light Engines

Heterogeneous integration is essential for the manufacturing of higher speed, lower power and highly compact optical components. In this talk we discuss heterogeneous optical integration, where separately manufactured electronic components are assembled on to an active silicon photonics interposer. This process allows for the integration of components independently designed and optimized from several different technology and foundry platforms, including semiconductor lasers onto a common active, optical interposer.

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Dr. Radha Nagarajan photo

Dr. Radha Nagarajan

SVP & CTO

Marvell Technology

Dr. Radha Nagarajan is Senior Vice President and Chief Technology Officer of Marvell’s Optical and Cloud Connectivity Group. In this role, he manages the development of the company’s optical platform technology and products. Radha joined Marvell from Inphi, where he served as the Senior Vice President and Chief Technology Officer of Platforms.

Radha has been awarded more than 240 US patents and is a Fellow of the IEEE, OSA and IET (UK). In 2006, he was awarded the IEEE/LEOS Aron Kressel Award and in 2022, the IPRM (Indium Phosphide and Related Materials) Award, in recognition of breakthrough work in the development and manufacturing of large scale photonic integrated circuits. In 2023, Radha was named to Electro Optics’ The Photonics100 2024 which honors the industry’s most innovative people. Radha holds a B.Eng. from the National University of Singapore, M.Eng. from the University of Tokyo, and Ph.D. from the University of California, Santa Barbara, all in Electrical Engineering.

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We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you.

Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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  • 15:00 – 15:20

Optical I/O Technology for the Future of AI

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Mark Wade photo

Mark Wade

CEO

Ayar Labs

Mark is Chief Executive Officer and Co-Founder of Ayar Labs. His prior roles at Ayar Labs include Chief Technology Officer and Senior Vice President of Engineering. He is recognized as a pioneer in photonics technologies and, prior to founding the company, led the team that designed the optics in the world’s first processor to communicate using light. He and his co-founders invented breakthrough technology at MIT and UC Berkeley from 2010-2015 which led to the formation of Ayar Labs. He holds a PhD from University of Colorado.

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Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by driving a 1000x improvement in interconnect bandwidth density at 10x lower power. Ayar Labs’ patented approach uses industry standard cost-effective silicon processing techniques to develop high speed, high density, low power optical based interconnect “chiplets” and lasers to replace traditional electrical based I/O. The company was founded in 2015 and is funded by a number of domestic and international venture capital firms as well as strategic investors. For more information, visit www.ayarlabs.com.

Address: 695 River Oaks Parkway, San Jose, CA 95134
Phone: 650-963-7200
Email: info@ayarlabs.com

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  • 15:25 – 16:25

Networking and Coffee Break Business Meeting Slot 3&4

Equipment / Materials Suppliers Update

  • 16:30 – 16:40

Enabling Metrology, Inspection and Lithography Technologies for AI and HPC Packaging

The increasing demand for advanced applications such as artificial intelligence (AI) and high-performance computing (HPC) has driven the greater adoption of the heterogeneous integration of chiplets into advanced packaging technologies. To optimize power, performance, area, and cost for specific applications, integration is pursued at both wafer and panel levels. In this presentation we will discuss key integration technology trends and examine how Onto Innovation’s comprehensive product portfolio addresses these high-value challenges.

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Dr. Monita Pau photo

Dr. Monita Pau

Strategic Marketing Director for Advanced Packaging

Onto Innovation

Dr. Monita Pau is Strategic Marketing Director for Advanced Packaging at Onto Innovation. Prior to joining Onto, she held various application engineering, marketing and strategic business development roles at DuPont and KLA. Her expertise spans across FOEL/BEOL process control solutions as well as advanced packaging and assembly materials serving both core and specialty semiconductor markets. Dr. Pau holds a Ph.D. degree in Chemistry from Stanford University.

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Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.

General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com

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  • 16:40 – 16:50

Wet Process and TBDB for Heterogeneous Integration

Wet process and TBDB (Temporary Bonding and Debonding) are important and critical for heterogeneous integration and advanced packaging.

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Eric Lee photo

Eric Lee

President of Sales Group

Scientech

Eric Lee is the President of Sales Group Scientech Corp. I have been working with Scientech Corp. since 2004. Prior to Scientech, Eric worked for UMC Taiwan and UMC Singapore from 1995 to 2004. Along with the role with Scientech, Eric is engaged with National Taiwan University of Science and Technology as a part-time professor in Advanced Packaging Master Program.

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Scientech Corporation was established in Taipei, Taiwan in 1979.

What we do: Industries we serve: Semiconductor (front-end, back-end and GaAs), Flat Panel Display, LED, Data Storage, Scientific Instruments and high-tech related industries.

Being a leading semiconductor equipment and wafer reclaim supplier in Taiwan, Scientech Corporation has launched the development of wet process equipment in 2003. Scientech has successively supported customers in LED, Mini/Micro LED, compound semi and power components such as IGBT, SiC and GaN industries, as well as advanced packaging process such as Bumping, Fan-out, Chip-On-Wafer and so on. Our wet process equipment has been successfully verified in the latest Chiplet’s 2.5D/3D packaging process technology and smoothly introduced into mass production.

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  • 16:50 – 17:00

Co-Packaged Optics and Solutions for High Volume manufacturing

The rapid development of AI, IoT, 5G and high-performance computing applications has led to exponential growth in data traffic within data centers. Nearly three-quarters of this data traffic remains within the confines of data centers. Traditional pluggable optics cannot keep up with this surge. This is where Co-Packaged Optics (CPO) technology comes into play.

CPO represents a disruptive approach to increasing bandwidth density and energy efficiency. It achieves this by significantly reducing electrical interconnect lengths through advanced packaging and simultaneously optimizing electronics and photonics. Particularly on the silicon platform, CPO holds promise for future data centers.

International companies such as Intel, Broadcom, and IBM have heavily invested in CPO technology. This interdisciplinary research field encompasses photonic devices, integrated circuit designs, packaging, modeling of photonic components, electronic-photonics co-simulation, applications, and standardization.

The challenges in CPO production are diverse. These include integrating electronics and photonics, developing reliable packaging technologies, and standardization efforts. Nevertheless, CPO offers tremendous potential for the future of data center connectivity.

ASMPT as a key equipment supplier for CPO applications offers the solutions for high volume manufacturing of Co-Packaged Optics devices.

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Dr. Johann Weinhändler photo

Dr. Johann Weinhändler

Managing Director

ASMPT Limited

Holds an Electrical Engineering Degree from the DAG Technikum in Würzburg/Germany , an MBA from the Open University Business School in Milton Keynes/UK and am Ph.D in Economics from the Trinity Colleges in Dublin. He has over 30 years global Sales and Marketing experience in the semiconductor equipment industry. During his career he was working with Lam Research, Datacon, Oerlikon Systems and ASMPT AMICRA.

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ASMPT, founded in 1975, is headquartered in Singapore and is listed in Hong Kong Stock Exchange since 1989.

ASMPT is the only company in the world that offers high-quality equipment for all major steps in the electronics manufacturing process – from carrier for chip interconnection to chip assembly and packaging to SMT. No other supplier offers a comparable range and depth of process expertise.

Semiconductor Solutions Segment Business of ASMPT offers a diverse product range from bonding to molding and trim & form to the integration of these activities into complete in-line systems for the microelectronics, semiconductor, camera modules, advanced packaging, photonics, and optoelectronics industries.

The group has successfully established itself as the leading player in the back-end assembly and packaging market with its innovative solutions and constant focus on customer value creation.

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  • 17:00 – 17:10

State-of-the art solutions for AI Chip manufacturing

Over the past nine months, the AI chip boom has accelerated considerably. High-bandwidth memory (HBM) chips, which are an essential part of AI chips, are undergoing rapid technological advancements. While temporary bonding will still be needed for wafer thinning of HBM3 chips and following generations, production of HBM chips is supposed to shift from thermal compression (TC) bonding to hybrid bonding solutions. TC may still be the preferred option for HBM4, as hybrid bonding is significantly more expensive. However, with HBM5 at the latest, the switch to hybrid bonding is expected to take place due to higher I/O densities. SUSS MicroTec has developed a D2W hybrid bonding solution together with flip-chip bonder specialist SET and also offers W2W hybrid bonding solutions, thus providing the technologies required for the next generations of HBM and AI chips.

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Robert Wanninger photo

Robert Wanninger

Senior Vice President Business Unit Advanced Backend Solutions

SUSS MicroTec

Robert Wanninger is Senior Vice President of the Advanced Backend Solutions (ABS) business unit at SUSS. With leading equipment and process solutions for Imaging, Coating and Bonding applications, SUSS ABS business unit is well positioned to serve the semiconductor industry. Robert brings ~25 years of experience in semiconductor industry. Prior to joining SUSS in 2021, he has worked over 20 years at Infineon in various management positions and spend two years in Korea as COO of LS Power Semitech. He holds a PhD in Chemistry from the University of Regensburg, Germany.

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SUSS MicroTec is a leading manufacturer of system and process solutions for micropatterning in the semiconductor industry and related markets. The company has more than 70 years of engineering experience and is a partner for high-volume production as well as for research and development. In close collaboration with research institutes and industry partners, SUSS MicroTec drives the development of next-generation technologies such as 3D integration and nanoimprint lithography as well as key processes for MEMS and LED production. With its global infrastructure for applications and service, SUSS MicroTec supports more than 8,000 installed systems worldwide. The headquarters of SUSS MicroTec is in Garching, near Munich, Germany.

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  • 17:10 – 17:20

The Impact of PulseForge’s Photonic Debonding on Temporary Bonding and Debonding Processes

PulseForge is at the forefront of semiconductor technology innovation. This presentation highlights our flagship photonic debonding (PDB) technology and its transformative impact on Temporary Bonding and Debonding (TB/DB) processes. PDB technology utilizes broadband light (200 nm – 1100 nm) from flashlamps, paired with an engineered light-absorbing layer, to achieve superior results in wafer thinning, Fan-out, and substrate transfer applications.

As TB/DB processes become increasingly prevalent, particularly with high-bandwidth memory chips and other advanced packaging applications, our presentation provides a comprehensive assessment of PDB’s effectiveness with thinned silicon wafers. We also offer a comparative yield analysis of devices as fab-out and post-TBDB processes with photonic debonding. Furthermore, we will emphasize the substantial cost of ownership benefits that PDB offers, demonstrating clear advantages of PDB over traditional debonding processes and making it a compelling choice for semiconductor manufacturers looking to enhance performance and reduce costs.
The PDB features a uniform, large-area illumination (75 mm x 150 mm), ensuring enhanced yield, high throughput, and cost-effectiveness for both wafer-level and panel-level packaging.

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Vikram Turkani photo

Vikram Turkani

Director, Technology Partnerships and Strategic Business Development

PulseForge

Vikram Turkani, serves as the Director of Technology Partnerships and Strategic Business Development at PulseForge Inc., a prominent technology company specializing in advanced packaging solutions based in Austin, Texas. In this pivotal role, Vikram is instrumental in steering the development and implementation of cutting-edge technologies at PulseForge. Through close collaboration with global technology partners, he ensures the successful transition of these state-of-the-art solutions into practical applications within the market.

Beyond driving the development of innovative technologies, Vikram actively engages with PulseForge’s customers, facilitating the seamless adoption of these innovations on a large scale. In addition to his professional pursuits, Vikram enjoys hiking Texas hill country and exploring the vibrant Austin food scene.

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We are experts in applied energy. PulseForge, Inc. designs and manufactures revolutionary pulsed-light systems for industrial processes. PulseForge utilizes applied energy in a precise and targeted manner to enable innovation in manufacturing. Our expertise and tools empower our customers to explore novel materials and manufacturing methodologies, driving dynamic and efficient production at scale.

Most semiconductor fab managers feel tremendous margin pressure, so PulseForge offers an innovative process that lowers TCO by over 30% while improving yield, so you can increase production while improving profitability. At PulseForge, we envision a future free of manufacturing limitations. A future where designers create freely and do not have to restrict or modify their designs in order to get them manufactured…a future where electronics can be integrated into textiles, plastics, and recycled materials easily, affordably, and in volume. A future with advances in semiconductors, additive manufacturing, packaging, drying, cleaning, and decontamination. Explore the possibilities www.pulseforge.com

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  • 17:20 – 17:30

Innovative laser assisted bonding processes for next generation advanced packaging

Conventional assembly techniques like thermo-compression bonding, oven reflow, or thermossonic wire bonding introduce high thermal and mechanical stress into the contacts and the entire semiconductor package, leading to warpage, cracks, or delamination effects. Moreover, the increasing significance of the IMC-layer becomes crucial when considering further miniaturization roadmaps of solder-based contacts << 16μm using these conventional bonding processes. To address this, “PacTech” has been developing laser-assisted processes since 1995, which enable high dynamic local and selective heating and are therefore ideal for next-generation advanced packaging. Laser-assisted reflow (LAR) of C4 bump arrays and SMD-populated substrates, laser-assisted chip bonding (LAB) and debonding processes (LAdB) as well as laser-soldered wire bonding (SB²-WB) for high-power devices, will be introduced and explained as alternative bonding solutions.

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Matthias Fettke photo

Matthias Fettke

VP Advanced Packaging Equipment

PacTech

  • Holding a Master´s degree in Laser- and Optical Technology from the University of Applied Science Ernst Abbe in Jena Germany
  • Expertise in integrating optical waveguides into thin glass sheets for photonic packaging and in laser bonding of photonic components acquired during his work at Fraunhofer IZM and IOF
  • He was jointly responsible for the production of the 1st generation of electrostatic chucks for ASML EUV lithography systems and worked for 8 years as leading senior product manager in the E-static Chuck production center in Berlin
  • For more than 10 years he is active in the field of semi-conductor packaging for PacTech. He is a specialist for laser-assisted bonding technologies and holds more than 50 patens and publications
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PacTech-Packaging Technologies GmbH, established 1995 and a group company of NAGASE & CO., LTD., manufactures equipment for the microelectronic & advanced packaging industry and offers wafer level bumping & packaging contract manufacturing out of Nauen, Germany (HQ), and through the 100% subsidiaries PacTech USA Inc., Silicon Valley, USA and PacTech ASIA Sdn., Bhd., Penang, Malaysia.

The equipment product line consists of solder jetting equipment (SB2-Jet), wafer-level solder ball transfer systems (Ultra-SB2), wafer-level solder rework equipment (Ultra-SB2 300 WLR), laser assisted (LAB, LCB, LAR) flip-chip bonders (Laplace) and automatic wet chemical lines for high volume electroless NiAu & NiPdAu bumping (PacLine 300 A50).

Those unique and highly innovative manufacturing systems are providing solutions for today’s tasks and challenges in advanced packaging applications.

The wafer level packaging & bumping subcontractor services consist of electroless Ni/Au, Ni/Pd and Ni/Pd/Au Under Bump Metallization (UBM) for either wafer level solder bumping for Flip Chip or WLCSP or for wire bonding. Additionally, PacTech offers AOI, X-Ray, SEM, BCB Repassivation, wafer-level redistribution, wafer backside metallization, wafer thinning, laser backside marking, wafer dicing, chip singulation, tape & reel services.

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Management Consultancy Session

  • 17:30 – 17:50

Disruptions in Semiconductor Supply Chain

a. We have been working with 3000+ global executives to reveal the level of disruption across various sectors and the driving force behind
b. The recent result shows semiconductor is experiencing more distruption than others
c. The driving forces behind are a few technology advancement, supply chain rebalancing driven geopolitical tension and customer demands
d. We have helped many of them take concrete actions to smooth the disruption from various topics
f. The key trends in supply chain rebalancing and our take-aways for TW semiconductor sectors

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Michael Mo photo

Michael Mo

Partner and Managing Director

AlixPartners

Michael is a proven business leader specializing in helping organizations drive business improvement through operation transformation and create sustainable growth. He brings more than 20 years of experience in strategy development and value creation and has served clients across a full spectrum of businesses, including high-tech and semiconductor sectors. Prior to joining AlixPartners, Michael was a Partner at EY-Parthenon and headed its strategy-to-transformation operation service line in APAC, He also held leadership roles in McKinsey, Johnson & Johnson and SAP. Michael holds a master’s degree in business administration from the IMD in Switzerland.

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AlixPartners is a results-driven global consulting firm that specializes in helping businesses respond quickly and decisively to their most critical challenges—from urgent performance improvement to complex restructuring, from risk mitigation to accelerated transformation. These are the moments when everything is on the line—a sudden shift in the market, an unexpected performance decline, a time-sensitive deal, a fork-in-the-road decision. We stand shoulder to shoulder with our clients until the job is done, and only measure our success in terms of the results we deliver.

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  • 17:50 – 17:55

Closing Address

Kamel Ait Mahiout photo

Kamel Ait Mahiout

President

ISES

Kamel Ait Mahiout is a seasoned professional with over 30 years of experience in the electronics industry. His expertise spans from RF and Microwave engineering to executive roles in prominent companies such as Unity SC and Amkor Technology, where he significantly contributed to the growth and alignment of the businesses with key industry players.

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International Semiconductor Executive Summits (ISES) holds a significant position within the semiconductor industry. Since 2010 we have scaled 8 major successful regional events globally. Our initiatives to date have been fully supported by local governments. For e.g., ISES USA is hosted in partnership with the Greater Phoenix Economic Council, ISES Taiwan is hosted in partnership with ITRI, ISES EU is hosted in partnership with the EU Commission, ISES Southeast Asia in partnership with Invest in Penang. We serve as a platform where senior executives in technology, manufacturing and R&D from various semiconductor companies, technology providers, and related industries gather to exchange information, shape strategies, and discuss the industry’s direction. Our summits have influenced industry trends and decisions due to the high-level discussions that take place.

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  • 18:15 – 18:30

Dinner Check-in on 3F Ballroom

  • 18:30 – 21:30

Gala Dinner Sponsored by Intel

  • Advisory Board Recognition
  • Member Welcome Ceremony
  • Entertainment

18:30 – 18:35 Intel Welcome Speech

Dr. Yu-Wen Huang photo

Dr. Yu-Wen Huang is an experienced technologist and system supply chain professional with more than 27 years of working in outsourced semiconductors industry. He is currently the Intel Hsinchu site manager, responsible for site operations and engaged in advanced packaging R&D. Prior to his current undertaking, he was instrumental in driving the assessment and adoption of the China Supply Chain ecosystem that supports various IA platforms like tablets, smart phones, and PC products in China. He led the Global Tech Ecosystem (GTE) Operations team that helped grow Client Computing China biz by enabling China Tech Ecosystem (CTE) ODMs to adopt IA PC roadmap platforms and achieve continuous revenue growth. In 2015 Yu-Wen’s was awarded the prestigious Intel Achievement Award (IAA) for being part of the team that drove 40Mu shipment of IA tablets in China. Before taking the China assignment in 2008, he had been managed Taiwan assembly/test outsourcing operations involving top tier foundries and OSATs for 8 years. Dr. Huang received his Ph.D. in Industrial Engineering from State University of New York, Binghamton. He then joined Institute of Microelectronics (IME), Singapore as Member of Technical Staff from 1997 to 2000, with primary focus on MCM-D module development, UBM characterization, and flip chip bumping process development. He also led FCBGA development programs in the IME initiated consortium.