• 07:50 – 08:30

Registration

  • 08:35 – 08:55

ISES Welcome Address

Kamel Ait Mahiout photo

Kamel Ait Mahiout

President

ISES

Kamel Ait Mahiout is a seasoned professional with over 30 years of experience in the electronics industry. His expertise spans from RF and Microwave engineering to executive roles in prominent companies such as Unity SC and Amkor Technology, where he significantly contributed to the growth and alignment of the businesses with key industry players.

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International Semiconductor Executive Summits (ISES) holds a significant position within the semiconductor industry. Since 2010 we have scaled 8 major successful regional events globally. Our initiatives to date have been fully supported by local governments. For e.g., ISES USA is hosted in partnership with the Greater Phoenix Economic Council, ISES Taiwan is hosted in partnership with ITRI, ISES EU is hosted in partnership with the EU Commission, ISES Southeast Asia in partnership with Invest in Penang. We serve as a platform where senior executives in technology, manufacturing and R&D from various semiconductor companies, technology providers, and related industries gather to exchange information, shape strategies, and discuss the industry’s direction. Our summits have influenced industry trends and decisions due to the high-level discussions that take place.

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ISES

Chiplet Ecosystem Acceleration: Strategy, Roadmap, and Standardization

  • 09:00 – 09:30

Keynote

TBC

Dr. Jun He photo

Dr. Jun He

VP Quality & Reliability, Advanced Packaging Technology & Service

TSMC

Dr. Jun He is Vice President of Quality & Reliability as well as Advanced Packaging Technology & Service at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). His responsibility spans across TSMC foundry eco-system and the Company’s backend business and operations management. Within the Q&R scope, his function covers incoming materials qualification, reliability and certification of new process technology & design IP, manufacturing quality as well as enabling customers for their product qualification and ramp. Besides overseeing all TSMC advanced packaging and testing manufacturing, his backend team is also accountable for key building blocks including bump/passivation/RDL process innovations and test technology development. Seamless collaboration and joint development with external partners across material, OSAT and substrate supply chain is one of his focus areas to enable customers’ product innovations at system level.

Prior to joining TSMC, Dr. He was a senior director at Intel Corporation, leading overall quality and reliability of process technology development and manufacturing. His scope included research & development of Si, advanced packaging and test along with Intel worldwide manufacturing operations.

Dr. He holds over 40 patents globally and published 50 papers in international conferences and peer-reviewed technical journals. He received his B.S. degree in Physics and Ph.D. in Materials Science from University of California, Santa Barbara.

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TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 281 distinct process technologies and manufactured 11,617 products for 510 customers in 2020 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 3-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan.

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TSMC
  • 09:30 – 10:00

Keynote

TBC

Koushik Banerjee photo

Koushik Banerjee

VP Technology Development Group

Intel

Koushik Banerjee is a vice president in the Technology Development Group at Intel Corporation and co-leads Assembly and Test Technology Integration. His organization is responsible for developing innovative, industry-leading packaging technologies for Intel and other customer products and transferring those technologies successfully into high-volume manufacturing. Koushik and his team also manage technology development in the external ecosystem supply chain for certain key ingredients that get integrated into Intel’s packaging. Banerjee holds more than a dozen patents in the field of microelectronic packaging. He earned his master’s degree in mechanical engineering from Georgia Institute of Technology.

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Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.

To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

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Intel
  • 10:00 – 10:30

Keynote

HBM (High Bandwidth Memory) and Advanced Packaging Technology for AI Era

The semiconductor packaging industry is expected to grow in the coming years, driven by the increasing demands for semiconductor chips in various applications, such as smartphones, autonomous vehicles, 5/6G, high-performance computing, IoT devices, and artificial intelligence. Another trend is the increasing adoption of heterogeneous integration, where different types of chips, such as CPUs, GPUs, and memory, are integrated into a single package to improve performance and reduce power consumption.

To overcome the limitations of performance/power/density/bandwidth of cutting edge systems, and to create new business opportunity and new values, the importance of advanced packaging technologies is more increased. For the above reasons, the future of the semiconductor packaging industry looks promising, with the increasing demand for semiconductor chips in various applications and the emergence of new packaging technologies driving growth and innovation in the semiconductor industry.

Major semiconductor players accelerate the competition to lead semiconductor industry hegemony by the evolution of advanced packaging technology such as chiplets and 2.5D/3D heterogeneous integration.

SK hynix drive the innovation of packaging technology to meet the demand for higher bandwidth and capacity of memory devices requiring in the increased AI workload applications such as the advent of ChatGPT, an artificial intelligence chatbot. High bandwidth memory (HBM), offers the largest capacity and bandwidth and also comes with the most improved power efficiency enabled by an advanced packaging technology of novel 3D chip stacking. SK Hynix is taking the lead in the HBM market. It developed the world’s first HBM in cooperation with AMD in 2013 and continuously released second/third/fourth-generation HBMs (HBM2/HBM2E/HBM3), and has secured a market share of 60-70 percent. The chip-let technology based on heterogeneous integration will be another key driver for memory-centric systems various combination of logic and memory devices. By the evolution of advanced packaging technologies, SK Hynix will continuously lead the competitiveness of memory business and prepare the business innovation for beyond memory era.

Kangwook Lee photo

Kangwook Lee

SVP and Head of PKG Development

SK Hynix

Dr. Lee has been one of critical leaders who are leading the era of 3D TSV stack memory such as HBM (High Bandwidth Memory) in semiconductor industry.

He has contributed broadly to, and led teams in, 3D integration/packaging R&D including core technology/product development/reliability study and mass production for HBM over 27 years.

Dr. Lee received the Ph.D. degree in machine intelligence and systems engineering from Tohoku University, Japan, in 2000. During his doctoral research at Tohoku University,

Dr. Lee proposed a new 3D-IC integration technology to achieve 3D devices with high performance and multi-functionality, leading this field in the world.

From 2001 to 2002, he was a Postdoctoral Researcher with the Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA.

He worked with Memory Division, Samsung Electronics Ltd., Korea, as a Principal Engineer from 2002 to 2008.

From 2008 to 2016, he worked with the New Industry Creation Hatchery Center (NICHe), Tohoku University, Japan, as a Professor.

From 2017 to 2018, he worked with R&D center, Amkor Technology Korea, as a VP.

He joined SK hynix 2018 and currently Senior VP, Head of PKG Development at SK Hynix, Korea.

Dr. Lee has led many interdisciplinary R&D programs on 3D integration, including integration of various materials and devices to achieve 3D devices/systems with high performance and new functionality,

3D-IC reliability research to investigate the impacts of 3D integration on the device performance and reliability, unique hybrid integration of nano-materials with Si, and product development of 3D stack DRAM

such as high-bandwidth memory (HBM). For over 27 years at universities and industries in Japan, US, and Korea, Dr. Lee has made exceptional technical contributions to and lasting impacts on 3D integration technology

and 3D product development in broad fields, such as material science, materials characterization/analysis, semiconductor device/process, electrical packaging, and Si micro-machining.

Dr. Lee has authored more than 230 scientific publications (peered journals, international conferences), co-edited 4 books, and given 43 tutorial/invited/keynote talks in international conferences including

IEEE IEDM, IEEE IRPS, VLSI Symposium, plus 23 US patent publications.

He has served as a frequent reviewer for a number of journals, including IEEE EDL, IEEE T- ED, IEEE CPMT, and technical program committees of international conferences, including IEEE ECTC, IEEE IRPS, IEEE EDTM, IEEE 3D SIC.

He is a Senior Member of IEEE.

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SK Hynix
  • 10:35 – 11:35

Networking and Coffee Break Business Meeting Slot 1&2

  • 11:40 – 12:00

Micron

Micron Technology, Inc.
  • 12:00 – 12:20

TBC

Dr. Bill En photo

Dr. Bill En

CVP, Foundry Technology and Operations

AMD

26 years of experience in the Semiconductor Industry ranging from silicon wafer R&D, process technology, circuit design and foundry technology with over 65 patents and 30 publications. He graduated from Univ. of California Berkeley with a Ph.D in Electrical Engineering and Computer Sciences in 1996. He is currently Corporate Vice President at Advanced Micro Devices overseeing Foundry technology from initial R&D through production for all AMD products.

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For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.

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AMD
  • 12:25 – 13:40

Buffet Lunch

  • 13:45 – 14:35

Panel Session: Standardization for Chiplet / Advanced Packaging

Moderator
Dr. Kuan-Neng Chen photo

Dr. Kuan-Neng Chen

Chair Professor

NYCU

NYCU

Dr. Kuan-Neng Chen is Chair Professor of Institute of Electronics in National Yang Ming Chiao Tung University (NYCU) in Taiwan. He received his Ph.D. degree in Electrical Engineering and Computer Science, and M.S. degree in Materials Science and Engineering, both from Massachusetts Institute of Technology (MIT). He was Vice President for International Affairs and Associate Dean of International College of Semiconductor Technology in NYCU, Program Director of Micro-Electronics Program in National Science and Technology Council in Taiwan, and a Research Staff Member at IBM Thomas J. Watson Research Center. 

Dr. Chen is the recipient of IEEE EPS Exceptional Technical Achievement Award, IMAPS William D. Ashmon – John A. Wagnon Technical Achievement Award, National Industrial Innovation Award, MOST Outstanding Research Award (2 times), MOST Futuristic Breakthrough Technology Award, NSTC Futuristic Breakthrough Technology Award, NCTU Distinguished Faculty Awards, NYCU/NCTU Outstanding Industry-Academia Cooperation Achievement Awards (7 times), Pan Wen Yuan Foundation Outstanding Research Award, CIE Outstanding Professor Award, CIEE Outstanding Professor Award, and IBM Invention Achievement Awards (5 times). He has authored more than 300 publications, including 3 books and 67 book chapters, and holds 87 patents. He was Guest Editor of MRS Bulletin and IEEE Transactions on Components, Packaging, and Manufacturing Technology. He served as General Chair of IEEE IITC and Program Co-Chair of IEEE IPFA, and committee member of IEDM, IEEE 3DIC, IEEE SSDM, IEEE VLSI-TSA, and IMAPS 3D Packaging. Dr. Chen is a Fellow of National Academy of Inventors (NAI), IEEE, IET, and IMAPS, and a member of Phi Tau Phi Scholastic Honor Society. 

In addition to his faculty position, Dr. Chen is Specially Appointed Professor of Tokyo Institute of Technology (Tokyo Tech) and Adjunct R&D Director in Industrial Technology and Research Institute (ITRI). Dr. Chen’s current research interests are three-dimensional integrated circuits (3D IC), advanced packaging, and heterogeneous integration. 

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NYCU was founded on the idea that, in a great university, people work across the disciplines to solve real-world problems. At our university, putting this idea into practice requires integrating Chiao Tung’s strengths in information and communications technology with Yang Ming’s strengths in biomedical research. It also requires contributing to fields located at the intersection of these research areas, for example, digital medicine and bioinformatics. And it requires training our students in such a way that the next generation will not be as constrained by disciplinary boundaries as the previous one.

At NYCU, we are striving to be a great university that transcends disciplinary divides to solve the increasingly complex problems that the world faces. We will continue to be guided by the idea that we can achieve something much greater together than we can individually. After all, that was the idea that led to the creation of our university in the first place.

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Panelist
Kam Lee photo

Kam Lee

eputy Head of TSMC Advanced Packaging Technology and Service.

TSMC

TSMC

Kam is currently the Deputy Head of TSMC Advanced Packaging Technology and Service. He joined TSMC earlier last year in March 2022 from Intel, where he served for 27 years in various roles in technology development, product development and high-volume manufacturing. Previously, he held the role as the Vice President and General Manager in Intel’s product engineering development group. At TSMC, Kam is actively working with his colleagues to advance the TSMC advanced packaging and testing technologies to serve its foundry customers.

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TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 281 distinct process technologies and manufactured 11,617 products for 510 customers in 2020 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 3-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan.

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Silicon-Photonics and Co-Packaged Optics Session

  • 14:40 – 15:00

TBC

Dr. Radha Nagarajan photo

Radha Nagarajan

SVP & CTO

Marvell

Dr. Radha Nagarajan is Senior Vice President and Chief Technology Officer of Marvell’s Optical and Cloud Connectivity Group. In this role, he manages the development of the company’s optical platform technology and products. Radha joined Marvell from Inphi, where he served as the Senior Vice President and Chief Technology Officer of Platforms.

Radha has been awarded more than 240 US patents and is a Fellow of the IEEE, OSA and IET (UK). In 2006, he was awarded the IEEE/LEOS Aron Kressel Award and in 2022, the IPRM (Indium Phosphide and Related Materials) Award, in recognition of breakthrough work in the development and manufacturing of large scale photonic integrated circuits. In 2023, Radha was named to Electro Optics’ The Photonics100 2024 which honors the industry’s most innovative people. Radha holds a B.Eng. from the National University of Singapore, M.Eng. from the University of Tokyo, and Ph.D. from the University of California, Santa Barbara, all in Electrical Engineering.

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Marvell
  • 15:00 – 15:20

TBC

Mark Wade photo

Mark Wade

CTO, SVP Engineering & Co-Founder

Ayar Labs

Mark is Chief Executive Officer and Co-Founder of Ayar Labs. His prior roles at Ayar Labs include Chief Technology Officer and Senior Vice President of Engineering. He is recognized as a pioneer in photonics technologies and, prior to founding the company, led the team that designed the optics in the world’s first processor to communicate using light. He and his co-founders invented breakthrough technology at MIT and UC Berkeley from 2010-2015 which led to the formation of Ayar Labs. He holds a PhD from University of Colorado.

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Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by driving a 1000x improvement in interconnect bandwidth density at 10x lower power. Ayar Labs’ patented approach uses industry standard cost-effective silicon processing techniques to develop high speed, high density, low power optical based interconnect “chiplets” and lasers to replace traditional electrical based I/O. The company was founded in 2015 and is funded by a number of domestic and international venture capital firms as well as strategic investors. For more information, visit www.ayarlabs.com.

Address: 3351 Olcott Street, Santa Clara, CA 95054
Phone: 650-963-7200
Email: info@ayarlabs.com

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Ayar Labs
  • 15:25 – 16:25

Networking and Coffee Break Business Meeting Slot 3&4

Equipment / Materials Suppliers Update

  • 16:30 – 16:40

Onto Innovation

Onto Innovation
  • 16:40 – 16:50

Scientech

Scientech

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