27-28 August 2025
Suwon
Salah Nasri
I.S.E.S.
Salah Nasri is the CEO & Co-Founder of the International Semiconductor Executive Summits (ISES), a division of the International Semiconductor Industry Group Ltd. an influential organization within the semiconductor industry. With extensive experience in the sector, Nasri has played a pivotal role in fostering global collaboration among semiconductor leaders. Under his leadership, ISES has become a premier platform for industry executives to connect, share insights, and drive innovation across various regions including the United States, Europe, Asia, and the Middle East.
Salah Nasri has been instrumental in expanding the reach and impact of ISES, organizing significant events that bring together decision-makers from across the semiconductor ecosystem. These events provide opportunities for networking, collaboration, and the exchange of ideas crucial for advancing the industry in areas such as semiconductor manufacturing, MEMS, AI, automotive electronics, and more.
His leadership has not only enhanced the visibility of ISES globally but also strengthened partnerships with key industry players, ensuring that ISES remains at the forefront of semiconductor innovation and development. Salah Nasri has previously worked at Goldman Sachs’s, Credit Suisse and International Business Development Group. Salah Nasri graduated from Oxford University and Loughborough University in International Relations and Economics. In 2024, Salah Nasri became a Stanford University Alumni after completing the Stanford Executive Program.
Company Profile
Established in 2010, the International Semiconductor Industry Group (I.S.I.G.) is a prestigious and trusted association within the semiconductor industry, renowned for orchestrating major regional summits across the globe, ranging from the U.S, the Middle East & Asia via our division, the International Semiconductor Executive Summits (I.S.E.S.). Our summits, are fully endorsed by local governments and leading companies in all areas of the semiconductor supply chain.
Moreover, I.S.E.S. serves as the Premier platform for senior executives in technology, manufacturing, and R&D from diverse semiconductor companies, technology providers, and affiliated industries. Our events are instrumental helping to shed light onto key industry trends, drive innovation and influence key decisions to help shape, and advance the growth of the semiconductor sector. Join us today!
08:10 – 08:30
Greater Phoenix: A Global Destination for Industrial Innovation
Greater Phoenix is home to an ever-expanding ecosystem of semiconductor manufacturing and its supply chain. Long-term strategic planning of resources at the state and regional level have supported this growth, ensuring that adequate water and nation-leading grid reliability meet the needs of industry. Paired with a robust workforce and an educational system anchored by Arizona State University and the Maricopa County Community College District, the region has the requisite labor force to meet the needs of key industry sectors. Greater Phoenix is a top global destination for businesses and uniquely positioned to seize the momentum of technological innovation and advanced industry to support future development.
Chris Camacho
Greater Phoenix Economic Council (GPEC)
Chris Camacho serves as president & CEO of the Greater Phoenix Economic Council (GPEC), one of the longest-standing public-private partnerships for economic development across the country. As chief executive, Chris leads the development and execution of the region’s strategic economic strategy, oversees domestic and international business development, and ensures the market position remains competitive through coordination with partner organizations, private sector leaders, and municipal and state leadership. GPEC has attracted more than 540 companies during his tenure, creating more than 100,000 jobs and $56.8 billion in capital investment. Some notable projects include TSMC, Apple, LG Energy Solutions, Microsoft, GoDaddy, Amazon, Garmin, General Motors, HelloFresh, KORE Power, Williams-Sonoma and headquarters including Benchmark Electronics, Carlisle Companies, Rogers Corporation and EMD Electronics. In October 2021, Chris led GPEC to being recognized as the top economicdevelopment organization globally by the International Economic Development Council a year after being named the top EDO in the U.S. in 2020.
Company Profile
Established in 1989, the Greater Phoenix Economic Council (GPEC) actively works to attract and grow quality businesses and advocate for the competitiveness of Greater Phoenix. As the regional economic development organization, GPEC works with 22 member communities, Maricopa County and almost 200 private investors to accomplish its mission, and serve as a strategic partner to companies across the world as they expand or relocate. Consistently ranked as a top national economic development organization, GPEC’s approach to connectivity extends beyond the fabric of the community. Known as The Connected Place, Greater Phoenix is in a relentless pursuit of innovative and entrepreneurial technology-focused companies that are committed to changing the game. As a result, over the past 32 years GPEC has fueled the regional economy by helping more than 895 companies, creating more than 163,000 jobs and $33.4 billion in capital investment.
Zachary Holman, Ph.D.
Arizona State University
Zachary Holman is an Associate Professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University, as well as the Director of Faculty Entrepreneurship within the Fulton Schools of Engineering. He received his Ph.D. in Mechanical Engineering from the University of Minnesota for his work on plasma-synthesized silicon and germanium nanocrystals, after which he spent two years as a postdoctoral researcher developing high-efficiency silicon solar cells at Ecole Polytechnique Fédérale de Lausanne in Switzerland. His research group at ASU focuses on new materials, processes, and device designs for high-efficiency silicon solar cells and silicon-based tandem solar cells. He has been named a Moore Inventor Fellow, Trustees of ASU Professor, Fulton Entrepreneurial Professor, and Joseph C. Palais Distinguished Faculty Scholar. He is the co-founder of two solar start-up companies (Sunflex Solar and Beyond Silicon) and an advanced materials start-up company (Swift Coat).
Company Profile
With 110,000+ undergraduate students, 30,000+ graduate and professional students, and 5,000+ faculty, Arizona State University (ASU) exemplifies a new prototype for the American public research university. At ASU, our culture of innovation and inclusion draws pioneering researchers to our faculty and attracts highly qualified students from all 50 states and more than 130 nations. ASU is expanding academic and entrepreneurial opportunities for every type of learner at all stages of life. Creating a resilient microelectronics innovation ecosystem is critical to America’s security and economic competitiveness. Arizona State University is responding to this need by working with industry and government partners to reestablish America’s capacity for domestic microelectronics and semiconductor manufacturing and innovation. ASU offers traditional degree programs and rapid, low-cost options for upskilling and re-skilling of the existing semiconductor workforce, as well as workers from outside the industry.
Company Products & Services
ASU is building the semiconductor talent pipeline and mobilizing the expertise and capabilities of the Fulton Schools of Engineering to drive research, development and innovation. The Fulton Schools of Engineering at Arizona State University is the largest and most comprehensive engineering school in the nation, offering 25 undergraduate degree programs, and 48 graduate degree programs. With over 30,000 students within the Fulton Schools of Engineering, 7000+ students studying microelectronics-related fields, and 150+ faculty engaged in microelectronics research and teaching. We offer extensive research facilities including our research in semiconductor manufacturing and advanced semiconductor packaging which is supported by our extensive lads which includes MacroTechnology Works with 250,000 total sq ft capacity, 43,000 sq ft clean rooms, and 23,00 sq ft wet/dry labs. We also offer graduate programs in semiconductor manufacturing, packaging, and assembly as well as certificate programs to support workforce development.
Darcy Renfro
Maricopa County Community College District
Darcy Renfro is Vice Chancellor of Community, Government Relations, & Economic Development for the Maricopa County Community College District (MCCCD). She oversees workforce and economic development strategies for MCCCD and advises the Chancellor on government and community affairs. MCCCD is one of the largest community college systems in the nation serving approximately 200,000 students and nearly 10,000 faculty and staff members across 10 colleges in the metropolitan Phoenix area. As part of the Chancellor’s executive team, Ms. Renfro is helping to lead the Maricopa Transformation to fundamentally transform the student experience to meet the education and employment needs of the community.
Prior to her current role, Ms. Renfro served as the policy advisor to Governor Janet Napolitano for workforce, economic development, and higher education, and was founding Director of The Arizona We Want Institute at the Center for the Future of Arizona where she was responsible for strategic direction and development of a series of “Progress Meters” to establish clear metrics for Arizona in achieving its citizens’ goals. She previously worked as the founding Director of the Arizona STEM Education Network at Science Foundation Arizona.
Ms. Renfro is a licensed attorney in Arizona and has practiced at the Phoenix offices of Fennemore Craig, P.C. Prior to law school, she worked on Capitol Hill for U.S. Senators Dennis DeConcini (AZ) and Howard Metzenbaum (OH).
Ms. Renfro is a native of Tucson and received both her undergraduate and Juris Doctor Degrees from the University of Arizona.
Darcy Renfro
Maricopa County Community College District
Darcy Renfro is Vice Chancellor of Community, Government Relations, & Economic Development for the Maricopa County Community College District (MCCCD). She oversees workforce and economic development strategies for MCCCD and advises the Chancellor on government and community affairs. MCCCD is one of the largest community college systems in the nation serving approximately 200,000 students and nearly 10,000 faculty and staff members across 10 colleges in the metropolitan Phoenix area. As part of the Chancellor’s executive team, Ms. Renfro is helping to lead the Maricopa Transformation to fundamentally transform the student experience to meet the education and employment needs of the community.
Prior to her current role, Ms. Renfro served as the policy advisor to Governor Janet Napolitano for workforce, economic development, and higher education, and was founding Director of The Arizona We Want Institute at the Center for the Future of Arizona where she was responsible for strategic direction and development of a series of “Progress Meters” to establish clear metrics for Arizona in achieving its citizens’ goals. She previously worked as the founding Director of the Arizona STEM Education Network at Science Foundation Arizona.
Ms. Renfro is a licensed attorney in Arizona and has practiced at the Phoenix offices of Fennemore Craig, P.C. Prior to law school, she worked on Capitol Hill for U.S. Senators Dennis DeConcini (AZ) and Howard Metzenbaum (OH).
Ms. Renfro is a native of Tucson and received both her undergraduate and Juris Doctor Degrees from the University of Arizona.
08:30 – 09:00
Keynote
Advanced Packaging Ecosystem
Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. This trend is set to continue as on-package heterogeneous integration of diverse IP from multiple process nodes and multiple foundries will enable new product concepts, decrease time to market and deliver cost/yield benefits. Additionally, novel 3D architectures and continued die-to-die interconnect scaling are opening previously un-achievable concepts for die partitioning and on-package capability integration. These technical challenges are requiring solutions across the ecosystem (Die/Package/Board/System) which provide opportunities for groundbreaking innovation. This presentation will highlight some of the key challenges the industry will have to jointly address to enable the 3D heterogeneous integration future, such as drivers in interconnect scaling, advanced substrate developments, and technologies to enable power and performance gains. A specific example of this is optical on-package integration, where Intel is taking an aggressive approach to enable highly scalable and manufacturable solutions with applicability beyond niche designs.
Dr. Babak Sabi, formerly Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development.
Babak joined Intel in 1984. Prior to leading ATTD, he oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices.
Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.
09:00 – 09:30
Keynote
Unleash Product Innovations with 3DFabric
With the development of 3DIC and associated packaging technologies, semiconductor industry has extended performance and density optimization to system level, complementary to traditional chip scaling. Amid broader adoption of TSMC’s advanced 2.5D/ 3D packaging solutions along with growing chiplet complexity and form factor, the interaction between Si, packaging and components become increasingly crucial and requires continue innovations on design, process development and manufacturing.
With 3DFabric Alliance, we are extending OIP collaboration to packaging/ testing and working with industry partners on substrate and memory technology development for integrated system-level design solution to customers, together with the ecosystem of OSATs, material and equipment suppliers. In parallel, we also establish the worldwide first fully automated factory to offer best flexibility for our customers to optimize their packaging solution with better cycle time and quality control.
Dr. Jun He
TSMC
Dr. Jun He is Vice President of Quality & Reliability as well as Advanced Packaging Technology & Service at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). His responsibility spans across TSMC foundry eco-system and the Company’s backend business and operations management. Within the Q&R scope, his function covers incoming materials qualification, reliability and certification of new process technology & design IP, manufacturing quality as well as enabling customers for their product qualification and ramp. Besides overseeing all TSMC advanced packaging and testing manufacturing, his backend team is also accountable for key building blocks including bump/passivation/RDL process innovations and test technology development. Seamless collaboration and joint development with external partners across material, OSAT and substrate supply chain is one of his focus areas to enable customers’ product innovations at system level.
Prior to joining TSMC, Dr. He was a senior director at Intel Corporation, leading overall quality and reliability of process technology development and manufacturing. His scope included research & development of Si, advanced packaging and test along with Intel worldwide manufacturing operations.
Dr. He holds over 40 patents globally and published 50 papers in international conferences and peer-reviewed technical journals. He received his B.S. degree in Physics and Ph.D. in Materials Science from University of California, Santa Barbara.
Company Profile
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
TSMC deployed 288 distinct process technologies, and manufactured 11,878 products for 522 customers in 2024 by providing the broadest range of advanced, specialty and advanced packaging technology services. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.
09:30 – 10:30
Networking Break & Business Meetings 1+2
10:30 – 11:00
Advanced Packaging: Enabling Moore’s Law’s Next Frontier
Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.
Raja Swaminathan, Ph.D.
AMD
Dr. Raja Swaminathan is the Corporate Vice President of Packaging at AMD, spearheading the development of AMD’s advanced packaging and heterogeneous integration roadmap. With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan’s expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple’s Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators. Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to their name, Dr. Swaminathan was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology.
Company Profile
For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.
11:00 – 11:10
Processing Innovations to Address the Manufacturing Challenges of Heterogeneous Integration
Heterogeneous design and integration has been referred to as the fourth stage in the evolution of Moore’s Law, as it enables us to integrate sets of chiplets into high performance computing packages with simultaneous improvements in power, performance, and area-cost. The need for high bandwidth and power-efficient interconnects between chiplets is driving new process technologies and automation technologies that address the higher feature densities and higher sensitivity to defects.
Large form factor panel-level processing enables higher manufacturing productivity at low cost but introduces several manufacturing challenges. The higher density of interconnections requires fine line capability that presents a challenge to traditional process equipment. Warping of the large and flexible substrates presents challenges both for handling the panels as well as the formation of reliable interconnects. The complexity of assembling multi-chiplet packages requires new factory automation solutions that can maximize product quality and factory utilization.
High resolution patterning can be achieved with materials and technologies from traditional front end processing, including PVD, Dry Etch, CVD and ALD. With its broad portfolio of semiconductor and display fabrication technologies and products, Applied Materials is addressing the challenge of delivering Front End manufacturing capability at Back End cost requirements. This presentation will highlight Applied innovations that enable panel level packaging and the factory of the future.
Len Tedeschi
Applied Materials
Len Tedeschi is vice president and general manager, Core Packaging Products at Applied Materials. Len is directly responsible for the Metals Packaging Products (MPP), Packaging Plating & Cleans (PPC), Tango & Plasma Dicing product groups. His focus is ensuring customers are successful with their current products, while simultaneously solving customer’s future high value problems.
Len has worked at Applied for >20 years and has over 27 years of semiconductor experience in roles ranging from product development & support, productivity, technical strategy, marketing, and general management. Len has worked with a variety of products and technologies including etch, deposition, lithography, metrology, and inspection.
Prior to joining Packaging, Len spent 14 years in Applied’s Etch Business Unit in a wide variety of customer focused positions. Len has >10 patents granted, mainly as the lead author.
Len began his career in 1995 as a lithography equipment engineer at IDT in Santa Clara, California.
He earned a bachelor of science degree in industrial technology from San Jose State University in 1995, where he served as captain of the university’s judo team, winning two collegiate national titles, and competing in the 1996 Olympic Judo Trials.
Company Profile
We are the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations Make Possible® a Better Future.
11:10 – 11:30
Bridging Front End, Packaging And Substrates To Advance The Semiconductor Roadmap
For over 50 years, Moore’s Law has defined the pace of the semiconductor industry with its ability to scale transistor density every 2 years. While the front end roadmap is still progressing thanks to EUV lithography and other process technology innovations, it’s no longer sufficient to keep pace with the diversified demand of the new digital society.
In recent years, we have seen an acceleration of technical innovations in IC packaging and IC substrates to complement front end wafer fabrication technologies and meet performance, power, and cost requirements.
The implementation of heterogeneous integration started long ago with the first multi-chip modules and 2D packages and is now accelerating with several new 2.5 and 3D architectures serving various end-applications, including high-performance computing, mobile, and networking, among others.
With interconnect geometry scaling, we see the need and the opportunity to bridge process equipment and process control methodologies across the three worlds of front-end, packaging and substrates. These once completely separated domains are becoming integrated just like the packages and systems they create.
The adoption of front end-like technologies and methodologies into packaging and IC substrates is not trivial and it requires innovation and customization to meet cost and performance requirements.
KLA is partnering with key industry players to bridge these three worlds and this presentation will show the challenges we are facing and problems we are solving to advance the semiconductor technology roadmap.
Keywords: Innovation, Advanced Packaging, Technology Roadmap, Heterogeneous Integration, Substrates
Oreste Donzella
KLA
Oreste Donzella serves as Executive Vice President and Chief Strategy Officer at KLA Corporation, leading key corporate growth initiatives and working closely with external stakeholders, such as financial investors and end customers in the broad electronics ecosystem.
Prior to his current role, Oreste was Executive Vice President, managing the Electronics, Packaging and Component (EPC) business group at KLA Corporation, which included multiple product divisions, targeting growth opportunities in specialty semiconductors, packaging, printed circuit board and display markets.
Previously, Oreste was the Chief Marketing Officer (CMO) of KLA. In this role, he oversaw corporate marketing activities, market analytics and forecast, and companywide collaborations with the broad electronics industry.
In the years before his CMO role, Oreste led the world-wide field applications engineering team, and was responsible for Customer Engagement projects and product portfolio optimization for wafer inspection platforms at KLA.
Previously, Oreste was Vice President and General Manager of the Surfscan and SWIFT divisions at KLA-Tencor. In these positions, he was responsible for the unpatterned wafer inspection, wafer geometry, and macro inspection business, overseeing new products development, sales, and marketing activities, customer support, and ultimately, division financial performance (P&L).
Oreste brings 30+ years of experience in the semiconductor industry. Prior to joining KLA in 1999, he spent almost seven years at Texas Instruments and Micron Technology, holding engineering and management positions in the process integration and yield enhancement departments.
Oreste holds various patents and is featured in several technical publications.
In 2020, Oreste was awarded with VLSI Semiconductor All Star for “charting KLA’s path into new markets related to More than Moore semiconductor technologies”
Oreste earned his master’s degree in electrical engineering from the University La Sapienza in Rome, Italy .
Company Profile
KLA develops industry-leading equipment and services that enable innovation throughout the electronics industry. We provide advanced process control and process-enabling solutions for manufacturing wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. In close collaboration with leading customers across the globe, our expert teams of physicists, engineers, data scientists and problem-solvers design solutions that move the world forward. Additional information may be found at kla.com
11:30 – 12:45
Buffet Lunch
Moderator
Curtis Zwenger
Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and Wafer Level packaging technologies. He was formerly responsible for Advanced System in Package product development. Curtis has authored numerous technical articles and papers, and he currently serves on the IMAPS Executive Council as Director of Membership. Curtis has been issued 35 US patents and holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix.
Panelist
Ahmer Syed
Qualcomm Technologies Inc.
Ahmer Syed is a VP of Engineering at Qualcomm in Global Manufacturing Technology and Operations organization. He leads a global team responsible for packaging technology development, NPI, HVM deployment for 5G, mobile, IoT, Connectivity, Automotive, and Compute markets.
A 30+ years veteran of Semiconductor and electronics industry, Ahmer has extensive experience in developing advanced packaging technologies such as Flip Chip, WLCSP, FO-WLP, Package on Package (PoP), QFN, and System in Package (SiP). He has authored and contributed to more than 70 technical papers and articles on advanced packaging and reliability and has been a keynote speaker in various international conferences.
Company Profile
Qualcomm is the world’s leading wireless technology innovator and the driving force behind the development, launch, and expansion of 5G. When we connected the phone to the internet, the mobile revolution was born. Today, our foundational technologies enable the mobile ecosystem and are found in every 3G, 4G and 5G smartphone. We bring the benefits of mobile to new industries, including automotive, the internet of things, and computing, and are leading the way to a world where everything and everyone can communicate and interact seamlessly.
Panelist
Tony LoBianco
Skyworks Solutions
Tony is Sr Director of Global Packaging for Skyworks Solutions. His teams lead advanced packaging R&D and production for wireless semiconductor products, including cellular, infrastructure, automotive, defense, IoT, and others.
He holds degrees in Chemical Engineering from the University of Illinois Champaign-Urbana and an MBA in Technology Management.
Company Profile
Skyworks Solutions, Inc. is empowering the wireless networking revolution. Our highly innovative analog semiconductors are connecting people, places and things spanning a number of new and previously unimagined applications within the automotive, broadband, cellular infrastructure, connected home, industrial, medical, military, smartphone, tablet and wearable markets.
Skyworks is a global company with engineering, marketing, operations, sales and support facilities located throughout Asia, Europe and North America.
Company Products & Services
Skyworks products are used in aerospace, automotive, broadband, cellular infrastructure, connected home, defense, entertainment and gaming, industrial, medical, military, smartphone, tablet, and wearable markets.
Panelist
Deepak Kulkarni
AMD
Deepak Kulkarni is a Fellow, Advanced Packaging at AMD. Deepak has over 15 years of experience in packaging technology development. Over the years, he has held several leadership positions driving substrate technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds 17 patents and nineteen publications on various aspects of packaging such as 2.5D/3D architectures, DFM/DFY and AI techniques applied to yield management. His contributions to the semiconductor industry have been recognized by an Intel Achievement Award, Next 5% award (AMD) and best paper award (ITHERM). Deepak holds a PhD from the University of Illinois Urbana-Champaign with a major in mechanical engineering and a minor in computational science.
Company Profile
For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.
Panelist
Intel Corporation
Rahul Manepalli is an Intel Fellow and Sr. Director of Module Engineering in the Substrate Package Technology Development Organization in Intel. Rahul and his team are responsible for developing next generation of materials, processes and equipment for Intel’s package pathfinding and development efforts. His team has been the driving force behind many of the technology innovations in Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and other substrate technologies. Rahul has also had an instrumental role in leading Intel’s assembly materials development and pathfinding efforts leading to several innovations in encapsulants, thermal interface materials and solder alloys. Rahul is the author of over 100 patent publications in semiconductor packaging, over 50 technical papers and invited talks and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.
Company Profile
Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.
To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.
13:25 – 13:55
A 360 View of Semiconductor Test from AI and Security Perspective
This keynote will explore the impact of deep learning including large language models on the semiconductor test. We will highlight the opportunities these models present for real-time data processing and discovery of insights, with specific applications in computer vision and natural language processing. However, the use of these models also introduces new security risks, particularly regarding the use of cloud infrastructure for collection of data, training and inference. By examining past attacks on networks, we will discuss the potential for malicious actors to steal data or intellectual property from companies. Attendees will gain an understanding of the opportunities and challenges in AI and security for the coming years and the importance of considering security measures in the development and deployment of these advanced solutions.
Claudionor Coelho
Advantest
Claudionor N. Coelho is the Chief Artificial Intelligence Officer and SVP of Engineering at Advantest, being responsible for AI strategy for Advantest and leading engineering for ACS.
Previously, he was the VP/Fellow for AI – Head of AI Labs at Palo Alto Networks, where he led AI and Neurosymbolic innovation for AIOps products at Palo Alto Networks. He also led the creation of next-generation time series analysis tools at scale (MLOps on GCP) integrated with knowledge graphs and formal technology.
He worked on Machine Learning/Deep Learning at Google. He is the creator of QKeras, a Deep Learning package for quantization on top of Keras with support for automatic quantization, being used by CERN (which made it to the cover page of Nature Machine Intelligence in August 2021). He was the VP of Software Engineering, Machine Learning, and Deep Learning at NVXL Technology. He did seminal work on AI at Synopsys Inc, and he opened the site for Cadence Design Systems in Brazil, being the GM for the site, following the acquisition of Jasper Design Automation, where he was the Worldwide SVP of R&D. Under his leadership, Jasper was awarded one of the most innovative companies in the US in 2013, according to Red Herring.
He created the initial strategy for Kunumi (when he was an angel investor), and he is an investor and is on the TAB of ConDati. He has more than 100 papers, patents, academic, and industry awards. He is currently an Invited Professor for Deep Learning at Santa Clara University, and previously, he was an Associate Professor of Computer Science at UFMG, Brazil, when he took the ACM Programming Contest to the Southern Hemisphere. He has a Ph.D. in EE/CS from Stanford University, an MBA from IBMEC Business School, and an MSCS and BSEE (summa cum laude) from UFMG, Brazil.
Company Profile
Advantest (TSE: 6857) is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors for applications including 5G communications, the Internet of Things (IoT), autonomous vehicles, artificial intelligence (AI), machine learning, smart medical devices and more. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also conducts R&D to address emerging testing challenges and applications, produces multi-vision metrology scanning electron microscopes essential to photomask manufacturing, and offers groundbreaking 3D imaging and analysis tools. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and an international commitment to sustainable practices and social responsibility. More information is available at www.advantest.com.
Company Products & Services
Advantest’s core product line, semiconductor test equipment, is used by IC manufacturers to test their semiconductors with high accuracy and efficiency, ensuring that they operate properly and meet performance and reliability requirements. The company uniquely provides one-stop shopping for the test cell, which includes test systems, test handlers, and device interfaces which are essential to semiconductor package test. In addition, Advantest Test Solutions offers a series of SLT and Burn-In solutions that can span from high mix/low volume applications to those that have the volume to require fully automated solutions, while Advantest’s SSD Test Systems allow customers to grow their product portfolios while remaining adaptable to the changing needs of the SSD market. The newly introduced Advantest Cloud Solutions™ (ACS) is an ecosystem of cloud-based products and technologies based on a single scalable data platform that allows customers to accomplish intelligent data-driven workflows. Advantest supports globally distributed semiconductor supply chains from locations around the world.
13:55 – 14:25
Package Design and Reliability Need in Server Systems
As power consumption in data-centers assumes increased importance, the role packaging and package reliability plays assumes a critical role. In this presentation we will review key trends in the server market, review various package technologies, modeling techniques as well as some innovative power solutions that are being implemented in servers.
Viresh Patel
Renesas Electronics
Company Profile
Renesas Electronics empowers a safer, smarter and more sustainable future where technology helps make our lives easier.
A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live.
14:25 – 15:25
Networking Break & Business Meetings 3+4
15:25 – 15:55
Navigating Through a Correction in the Semiconductor Market
Mario Morales
IDC
Mario Morales is the group vice president of IDC’s enabling technologies, semiconductor, storage, and DataSphere research.
He is responsible for in-depth analysis, evaluation of emerging markets and trends, forecasting, and research of major semiconductor industry segments such as embedded and intelligent systems, wireless, personal computing, networking and cloud infrastructure, automotive electronics, and AI semiconductors.
BACKGROUND
Mr. Morales is an accomplished program vice president, manager, and industry expert with over 25 years of experience in building a multinational top-tier consulting, sales, and research team and driving a set of established businesses. Solid experience in managing strategic partnerships and advisory services with IDC’s largest multinational clients. Strong analytical, strategic planning skills, and managing complex projects involving strong collaboration across geographies, functional groups, and business units. Proven leadership skills and instrumental at establishing research and business KPIs.
Mr. Morales is a trusted advisor to leading high tech company executives, financial investors, and bankers on market landscape and direction, product and technology positioning, competitive benchmarking, M&A, HW, and SW technology, and brand health and sustainability. Established relationships with technology suppliers including Intel, Samsung, TSMC, Qualcomm, Huawei, HP, AMD, NVIDIA, Microsoft, Facebook, TI, Micron, UMC, SoftBank, ARM, NXP, and others.
Mr. Morales is the leading advisor and expert analyst for IDC’s largest Wall Street clients including investment banking, VC’s, and mutual and hedge funds across every major financial region.
Over his career, Mr. Morales has authored and co-authored over 240 reports and studies in the area of semiconductors, mobile, PC, wireless, embedded, IoT, and IT marketplace. His team is responsible for some of the most interesting and evolving tech in our industry including coverage of microprocessors, accelerated computing, storage, memory, sensors and connectivity. His team has been responsible for initiating coverage of emerging technologies for IDC, and driving new research business practices, and creating leading industry market models in DRAM, NAND, Embedded processors and controllers, AI ML architectures, cellular baseband modems, WiFi, cellular broadband, digital consumer, foundry, EMS, and intelligent systems.
His career includes past positions with NEC Electronics and Dataquest.
EDUCATIONAL ACCOMPLISHMENTS
Company Profile
IDC is the premier global provider of market intelligence, advisory services, and events for the information technology, telecommunications, and consumer technology markets. IDC helps IT professionals, business executives, and the investment community make fact-based decisions on technology purchases and business strategy. More than 1,100 IDC analysts provide global, regional, and local expertise on technology and industry opportunities and trends in over 110 countries worldwide. For more than 50 years IDC has provided strategic insights to help our clients achieve their key business objectives. IDC’s Insights businesses provide industry-focused advice for IT buyers in the Financial, Government, Health, Retail, Manufacturing and Energy verticals. IDC is a subsidiary of IDG, the world’s leading technology media, research, and events company. You can learn more about IDC by visiting www.idc.com.
15:55 – 16:05
Not All Nanograined Copper Is Created Equal
Previously we have demonstrated that electroplated copper could be engineered to have microstructures at um and nm scales. This paper shows that not all nanograined copper is created equal. Through systematic investigations, significant insight is obtained into the necessary conditions to create a stable nanograined copper that meets the following criteria: 1. microstructure stable over 9 months at ambient storage conditions, 2. textures of the electrodeposited copper do not depend on substrate types and their textures, 3. grain growth increases to micron scale at temperatures above 150 C. Furthermore, we shall introduce a concept of nanograin threshold in the context of RT microstructure stability.
Dr. Yun Zhang
Shinhao Materials
Dr Yun Zhang, founder and CEO of Shinhao Materials LLC, has been active in materials innovation, R&D, marketing and sales for over 28 years, holding 34 granted patents, and numerous peer-reviewed journal publications and awards. She started her career at AT&T Bell labs in 1994, carrying out materials research and development. Her work on tin whisker growth won international recognition for demonstrating experimentally for the first time its driving force and for developing mitigation solutions. In 2002, she was appointed global R&D director by Cookson Electronics Enthone for its electronics business. In the subsequent 10 years, her insight and leadership in fundamental understanding of electrodeposition process at a molecule level, combined with a deep appreciation of technology trends and customer needs has won Dr. Zhang many friends and willing partners at top tier equipment manufacturers and key customers. Those close and collaborative partnerships resulted in win-win to all parties for RDL, copper pillar and TSV plating. She received a BS in chemistry from Nanjing University, and a PhD in chemistry from Brown University.
Company Profile
Shinhao Materials LLC is located in Suzhou China. Its mission is to invent and produce new materials to meet the ever-changing needs of the semiconductor industry, to service its customers in timely and cost-effective way. Being technology heavy, asset light, it has focused on technology innovation. Through its relatively short life, it has developed several unique classes of copper plating additives that have shown to be effective in addressing electrical, thermal, and stress challenges we are facing today. Its IntraCu® products are patent-protected in US, Korea, Taiwan and mainland China. In 2019, Shinhao Materials formed a strategic partnership with Umicore EP to sell and service its customers better internationally.
16:05 – 16:15
Valuation of Artificial Intelligence for Semiconductor Equipment
Applications for Artificial Intelligence (AI) have grown substantially over the last few years in the legal, medical, and automotive industries. These business sectors are regulated more heavily than semiconductor manufacturing equipment is, but use of AI in the semiconductor industry is lagging. The costs and benefits of AI are relatively easy to project, so it follows that AI has been studied and found that large-scale adoption provides an insufficient return on investment. A cost model will be proposed showing likely AI growth areas such as automated maintenance tasks and performance benchmarking, and a few that may remain out of reach.
Jon Hander
ASMPT Limited
Jon Hander is Assistant Vice President of Panel Products for ASM NEXX. He has worked at NEXX since 2011 and in the semiconductor industry since 1996. In his career, Jon has served in manufacturing, service, process, sales, development & product management roles. Jon has a BS in Engineering Technology from Texas A&M University.
Company Profile
ASMPT, founded in 1975, is headquartered in Singapore and is listed in Hong Kong Stock Exchange since 1989.
ASMPT is the only company in the world that offers high-quality equipment for all major steps in the electronics manufacturing process – from carrier for chip interconnection to chip assembly and packaging to SMT. No other supplier offers a comparable range and depth of process expertise.
Semiconductor Solutions Segment Business of ASMPT offers a diverse product range from bonding to molding and trim & form to the integration of these activities into complete in-line systems for the microelectronics, semiconductor, camera modules, advanced packaging, photonics, and optoelectronics industries.
The group has successfully established itself as the leading player in the back-end assembly and packaging market with its innovative solutions and constant focus on customer value creation.
16:15 – 16:25
Advanced Packaging Materials and Evaluation Platform at Resonac
Resonac has started Packaging Solution Center as new R&D center to propose one-stop solution for customers in 2018 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package in October, 2021.
2.xD and 3D packages require to connect chips and components in high density, therefore, both wiring pitch and vertical interconnect dimension must be finer and finer. At the same time, in order to achieve better performance, more and more chips are integrated together and thus the package size is increasing. To meet these requirement, we are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large 2.5D advanced package.
The presentation will cover the significance and strengths of JOINT2, and updates on research and development.
Hidenori Abe
Resonac Corporation
Hidenori Abe CTO for semiconductor materials, Resonac Holdings Corporation Executive director, Electronics Business Headquarters, Resonac Corporation. He is leading electronics materials R&D and strategy for semiconductor, substrate and display. Until 2023, he was the head of Electronics R&D Center and Packaging Solution Center, which is open innovation hub in advanced packaging development. I launched JOINT2, new advanced packaging consortium targeting 2.xD and 3D package in 2021.Prior to the above mission, he have been a General Manager of CMP Slurry Business Sector for three years. Before that he was a Manager of Marketing Promotion Group in Innovation Promotion Center at Hitachi Chemical (HC) for 2 years. When the career, he was promoted new R&D projects, especially targeting new business field using new technologies, and also to promote developing R&D products. As a side note, HC is one of the merged companies of Resonac. Hidenori Abe was Manager of Business Development Group in Packaging Solution Center at HC for 1 year with responsibility to promote open laboratory to partners such as customers and equipment makers, responsibility of marketing wearable related materials. Before that, he was epoxy molding compounds (EMC) engineer. During his 16 years carrier as engineer, he spent time doing responsibility of development of non-conductive carbon, green EMC, Cu wire compatible EMC, wafer level compression compounds, power module EMC and so on. His Cu wire compatible EMC development work contributed to the promotion to Cu wire conversion through several published papers. He received a master degree in chemical engineering field from Tokyo Institute of Technology, Japan and a master degree at the EMBA course from Oxford, UK.
Company Profile
Resonac defines its purpose as “Change society through the power of chemistry.” Resonac aims to be a world-class functional chemical manufacturer, creating functions necessary for the times, supporting technological innovation, and contributing to the sustainable development of our customers. Resonac is Global Leading semiconductor materials supplier. In order to achieve technological innovation for solving various social issues, it is essential for us to make wide-ranging co-creative efforts with partners, and Resonac is open to collaboration including 1on1 co-development with any partner.
We have opened a Packaging Solution Center and are actively engaged in next-generation semiconductor co-creation activities through JOINT2 with many partner companies. Furthermore, starting this year, we will also seek co-creation opportunities in the United States by launching US-JOINT.
16:25 – 16:30
AICS Solutions to High Value Problems
The “More than Moore” era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75 mm x 75 mm to 175 mm x 175 mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges for advanced IC substrates. The large package size reduces the number of units per panel, making the panel yield of paramount importance. In addition, with the increasing number of RDL layers, alignment shift per buildup step, due to the process induced substrate distortion can lead to a steady overlay drift and increase the RDL total interconnect length to a point where it exceeds the resistance specification. Solutions to these high value problems will be the subject of this talk.
Keith Best
Onto Innovation
For more than 35 years, Keith Best has held a range of semiconductor processing and applications positions for both device manufacturing and capital equipment companies, of which 13 years were with ASML where he held the position of Director, Applications Engineering. Most recently, Keith was Advanced Packaging Process Development Engineering Manager at SkyWater Florida. He is currently the Director of Product Marketing, Lithography, at Onto Innovation supporting the JetStep® advanced packaging lithography stepper. Keith holds a B.Sc. Honors Degree in Materials Science from the University of Greenwich, UK. He has numerous publications and holds 22 US patents in the areas of photolithography and process integration.
Company Profile
Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.
General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com
Dr. Shekhar Chandrashekhar
iNEMI
Shekhar Chandrashekhar has over 30 years’ experience as a leader, strategist, and innovator with a history of driving improvements that streamline operations, drive growth and increase profitability on a global scale.
Prior to joining iNEMI, Shekhar was responsible for managing the national network of Smart Manufacturing Innovation Centers (SMICs) for the Clean Energy & Smart Manufacturing Institute (CESMII). He has also worked with the American Society of Mechanical Engineers (ASME) as managing director, programs, for the association’s executive leadership team. Shekhar began his career as a member of technical staff of AT&T Bell Labs and held several management positions with Bell Labs/Lucent Technologies/Alcatel-Lucent, including senior manager for the Network Solutions Group and Bell Labs/Supply Chain Networks. He eventually became director of the company’s CTO Group, where he created the footprint for Global Engineering Centers.
He received the Advanced Technology Excellence Award from Bell Laboratories and the Outstanding Young Manufacturing Engineer Award from SME. He has published over 25 papers in international journals and conferences.
Moderator
Amy Leong
FormFactor
Amy Leong has been with FormFactor since October 2012. Prior to this, Amy was the VP of Marketing at MicroProbe from April 2010 through the October 2012 closing of FormFactor’s acquisition of MicroProbe. Before joining MicroProbe, Ms. Leong worked at Gartner, Inc. as a Research Director from 2008 to 2010 and covered the ASSP system-on-chip and microcontroller markets. From 2003 to 2008, Ms. Leong worked at FormFactor where she served as Senior Director of Corporate Strategic Marketing and Director of DRAM Product Marketing. Prior to FormFactor, Ms. Leong worked in a variety of semiconductor process engineering and product marketing roles at KLA-Tencor and IBM.
Ms. Leong holds an M.S. in Material Science and Engineering from Stanford University and a B.S. in Chemical Engineering from the University of California, Berkeley.
Company Profile
FormFactor is a leading provider of essential test and measurement technologies along the full IC life cycle – from characterization, modeling, reliability, and design debug, to qualification and production test. Semiconductor companies rely upon FormFactor’s products and services to accelerate profitability.
FormFactor’s leading-edge probe stations, probes, probe cards, advanced thermal subsystems, quantum cryogenic systems and integrated systems deliver precision accuracy and superior performance both in the lab and during production manufacturing.
Visit www.formfactor.com or follow us on LinkedIn.
Panelist
Dr. Ann Kelleher
Intel Corporation
Dr. Ann Kelleher is the executive vice president and general manager of Technology Development at Intel Corporation. Since 2020, she is responsible for the research, development and deployment of the next-generation silicon, advanced packaging, and test technologies that power Intel’s innovation. She joined Intel in 1996 as a process engineer and has worked in areas spanning from litho, thin films, yield, to managing all of Intel’s Global operations including Fab and Assembly Test factories, supply chain and construction. She did her Ph.D. in electrical engineering from University College Cork in Ireland and her post-doc at IMEC.
Company Profile
Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.
To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.
Panelist
Najwa Khazal
Najwa Khazal has more than 20 years’ experience in the delivery of business transformation programs across a range of industries, including energy, aerospace and automotive, in America, China, EMEA, India and Mexico. Her successful track record in driving value creation programs spans supply chain management, product lifecycle management, process integration, digital transformation and organizational change.
Najwa joined Edwards as General Manager for the Service Technology Centres (STC) Americas organisation in April 2021, responsible for defining, implementing and facilitating the strategic initiatives needed to support the future growth of Edwards and its customers in the semiconductor industry. Najwa has responsibility for the operational performance and management of remanufacturing facilities located in Glenwillow and Hillsboro in the US, Nogales in Mexico, and Sao Paulo in Brazil.
Prior to joining Edwards, Najwa was General Manager for Collins Aerospace.
Najwa has a broad education, achieving a distinction from the Harvard Business Analytics Program, a Master of Business Administration and a Bachelor of Science in Mechanical Engineering Technology.
Najwa is a passionate advocate for STEM (science, technology, engineering, maths) education, and has spent more than a decade facilitating international business and organizational development classes for undergraduate and master level students.
Najwa is a US citizen and is based in Arizona.
Panelist
Christine Dunbar
Christine Dunbar, formerly Senior Vice President of Global Sales at IQE, the leading supplier of compound semiconductor wafer products and advanced material solutions to the global semiconductor industry. Christine joined IQE in August 2022.
Christine was previously at GlobalFoundries where she held various executive roles driving GF business growth towards the October 2022 IPO. She joined GlobalFoundries in July 2015 with the IBM Microlectronics Division acquisition, as the Vice President of Product Management for the RF Business Unit.
Christine graduated from Cornell University in 1996 with a bachelor’s degree in Materials Science and Engineering and has held various engineering, technical management, and executive positions throughout her career, including leadership roles in Sales, Business Development & Semiconductor Manufacturing Operations. In 2018 Christine was nominated for the Global Semiconductor Association’s inaugural “Rising Woman of Influence” award.
Christine is passionate about serving as an ambassador for her employers and the semiconductor industry writ large thru active participation and speaking engagements at various industry forums. Christine is also a passionate advocate for women in semiconductors, and has sponsored the establishment of women’s resource groups at IBM, GlobalFoundries and IQE.
Christine is also active in her community supporting causes important to her. She is a founding member of the Leadership Now Project, a group of non-partisan business leaders committed to the health of the US democracy, established in 2017. Christine also serves on the Board of Directors at the Boys and Girls Club of Burlington, Vermont. She lives in Shelburne, Vermont USA with her partner & two teenage children.
Panelist
Deca Technologies
Robin Davis is the Director of Business Development at Deca Technologies, an industry leading semiconductor interconnect solutions company. She focuses on identifying new opportunities for the powerful miniaturization and performance benefits of Deca’s M-Series and Adaptive Patterning Technologies. Additionally, she works closely with both internal and customer R&D teams to drive next generation products and technological advances. She is both a contributor and lead inventor on many of Deca’s patents. Previously, Robin fulfilled the role of Senior Solutions Architect at Deca, where she collaborated with customers, suppliers, and Deca’s engineering team to advance package design and interconnect solutions. Robin started her career as a semiconductor packaging engineer at Lattice Semiconductor before transitioning to Advanced Packaging Tools Technical Marketing Engineer at Mentor Graphics (now Siemens EDA). Robin graduated with her BSEE from Portland State University. She is a member of the Tau Beta Pi and IEEE Eta Kappa Nu Honor Societies. Robin also serves as chair of the Diversity, Equity and Inclusivity committee for the International Microelectronics and Packaging Society (IMAPS).
Company Profile
Deca is the semiconductor industry’s leading independent development, implementation and licensing provider of advanced packaging technology offering M-Series, the #1 volume fan-out technology and Adaptive Patterning, empowering designers with breakthrough ultra-high-density interconnect capability.
18:00 – 19:00
Cocktail Reception Sponsored by Green Technology Investments LLC (GTI)
Tal Levin
GTI (Green Technology Investments)
Tal Levin serves as the Executive Vice President at Green Technology Investments LLC (GTi), headquartered in Scottsdale, Arizona, USA. GTI specializes in AMAT Metrology, encompassing a range of cutting-edge technologies such as SEMVision, Defect Review “DR-SEM,” VeritySEM, Critical Dimension SEM “CD-SEM”, and Compass & ComPLUS, Darkfield Inspection systems.
Having co-founded GTI in 2012, Tal has played a pivotal role in driving global sales initiatives until recently, when he shifted his focus to overseeing the technology roadmap and strategic procurement activities for both domestic and international clients.
In line with GTI’s growth strategy in 2023, the company underwent a transformation, establishing two distinct divisions: Metrex and RT-Ex. Additionally, GTI secured exclusive representation rights for the etrology™ software measurement solutions.
With over 32 years of experience in the semiconductor industry, Tal Levin is a seasoned executive with a profound understanding of semiconductor processes. His expertise extends to establishing and managing global service and sales networks, particularly in key regions such as China, Taiwan, and Southeast Asia.
Throughout his extensive career, Tal has held significant positions at notable companies including H.T.M., Norcimbus Inc., OEM Group, and GTI, where he and the team have developed several patent applications aimed at process enhancement and measurement refinement.
Tal Levin exemplifies excellence in management, strategic planning, and international business development within the semiconductor industry, serving as a benchmark for leadership and innovation.
Company Profile
Green Technology Investments LLC (GTi), headquartered in Scottsdale, Arizona, is a pioneering force in the semiconductor industry. With a focus on innovative remanufacturing and software solutions, GTi aims to revolutionize how businesses access advanced technology. Since its inception, in 2012, GTi has been committed to providing high-quality equipment and expert services to its global clientele. With offices strategically located in North America, Europe, and Asia, GTi is well-positioned to meet the needs of customers worldwide. By investing in research and development, GTi continues to expand the capabilities of remanufactured equipment and software, making cutting-edge technology more accessible and affordable for businesses of all sizes. GTi’s impact on the semiconductor industry is profound, enabling businesses to compete effectively in today’s dynamic market landscape.
Company Products & Services
Green Technology Investments LLC (GTi) offers a comprehensive range of products and services tailored to the semiconductor industry’s evolving needs. Specializing in remanufacturing and software solutions, GTi provides access to advanced technology at a more affordable price point. Their product lineup includes remanufactured semiconductor equipment such as CD-SEM, DR-SEM metrology systems, and MASK systems, ensuring high-quality performance and significant cost savings compared to new systems. In addition to equipment, GTi offers ready-to-ship spare parts, expert service support, and foundry capabilities to enhance customer experience and satisfaction. With a relentless focus on innovation and customer satisfaction, GTi is dedicated to empowering businesses of all sizes with the tools they need to thrive in today’s competitive global market.
19:00 – 21:00
Gala Dinner Sponsored by TEL
+ Industry Awards Ceremony
Mark Dougherty
Tokyo Electron
Mark is President and General Manager of TEL Manufacturing and Engineering of America (TMEA), a group company of Tokyo Electron Limited.
Prior to joining TEL in April 2020 he was the VP of module engineering and manufacturing operations at GLOBALFOUNDRIES Fab 8, where he led a 10X increase in manufacturing capacity, ramping production volume and yield to world class levels.
Mark spent over 20 years in IBM’s semiconductor unit, working as a process and integration engineer before holding progressively larger management responsibilities in module engineering, process control, manufacturing operations, and unit process development.
He holds a BS in Chemical Engineering from Clarkson University, where he was formerly a member of the Industry Advisory Board for the Center for Advanced Materials Processing (CAMP), and currently serves as the chair of the Dean’s Leadership Council for the Wallace H Coulter School of Engineering.
Mark and his wife Amy reside in Minneapolis, and have four children.
Company Profile
As a leading global company of semiconductor and flat panel display (FPD) production equipment, Tokyo Electron Limited (TEL) engages in development, manufacturing, and sales in a wide range of product fields. Building on the technological expertise and know-how that we have been cultivating since our inception over 50 years ago, we strive to contribute to the development of a dream-inspiring society. All of TEL’s semiconductor and FPD production equipment product lines maintain high market shares in their respective global segments. TEL provides outstanding products and services to customers through a global network in the U.S., Europe, and Asia.
Website: https://www.tel.com/
Phone: +1-512-424-100
Additional Contact Information: https://www.tel.com/contactus/
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