• 08:00 – 08:10

Welcome Speech

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Salah Nasri

President

ISES

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International Semiconductor Executive Summits (ISES) holds a significant position within the semiconductor industry. Since 2010 we have scaled 8 major successful regional events globally. Our initiatives to date have been fully supported by local governments. For e.g., ISES USA is hosted in partnership with the Greater Phoenix Economic Council, ISES Taiwan is hosted in partnership with ITRI, ISES EU is hosted in partnership with the EU Commission, ISES Southeast Asia in partnership with Invest in Penang. We serve as a platform where senior executives in technology, manufacturing and R&D from various semiconductor companies, technology providers, and related industries gather to exchange information, shape strategies, and discuss the industry’s direction. Our summits have influenced industry trends and decisions due to the high-level discussions that take place.

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ISES
  • 08:10 – 08:30

Greater Phoenix: A Global Destination for Industrial Innovation

Greater Phoenix is home to an ever-expanding ecosystem of semiconductor manufacturing and its supply chain. Long-term strategic planning of resources at the state and regional level have supported this growth, ensuring that adequate water and nation-leading grid reliability meet the needs of industry. Paired with a robust workforce and an educational system anchored by Arizona State University and the Maricopa County Community College District, the region has the requisite labor force to meet the needs of key industry sectors. Greater Phoenix is a top global destination for businesses and uniquely positioned to seize the momentum of technological innovation and advanced industry to support future development.

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Chris Camacho

President & CEO

Greater Phoenix Economic Council (GPEC)

Chris Camacho serves as president & CEO of the Greater Phoenix Economic Council (GPEC), one of the longest-standing public-private partnerships for economic development across the country. As chief executive, Chris leads the development and execution of the region’s strategic economic strategy, oversees domestic and international business development, and ensures the market position remains competitive through coordination with partner organizations, private sector leaders, and municipal and state leadership. He has led the attraction of more than 460 companies during his tenure, creating nearly 85,000 jobs and $24 billion in capital investment. Some notable projects include TSMC, Apple, Silicon Valley Bank, Microsoft, GoDaddy, Yelp, Amazon, Garmin, General Motors, ElectraMeccanica, Zoom, HelloFresh, and headquarters including Benchmark Electronics, Carlisle Companies and Rogers Corporation. In October 2021, Chris led GPEC to being recognized as the top economic development organization globally by the International Economic Development Council a year after being named the top EDO in the U.S. in 2020.

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Established in 1989, the Greater Phoenix Economic Council (GPEC) actively works to attract and grow quality businesses and advocate for the competitiveness of Greater Phoenix. As the regional economic development organization, GPEC works with 22 member communities, Maricopa County and almost 200 private investors to accomplish its mission, and serve as a strategic partner to companies across the world as they expand or relocate. Consistently ranked as a top national economic development organization, GPEC’s approach to connectivity extends beyond the fabric of the community. Known as The Connected Place, Greater Phoenix is in a relentless pursuit of innovative and entrepreneurial technology-focused companies that are committed to changing the game. As a result, over the past 32 years GPEC has fueled the regional economy by helping more than 895 companies, creating more than 163,000 jobs and $33.4 billion in capital investment.

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Greater Phoenix Economic Council (GPEC)
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Zachary Holman, Ph.D.

Associate Professor and Director of Faculty Entrepreneurship

Arizona State University

Zachary Holman is an Associate Professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University, as well as the Director of Faculty Entrepreneurship within the Fulton Schools of Engineering. He received his Ph.D. in Mechanical Engineering from the University of Minnesota for his work on plasma-synthesized silicon and germanium nanocrystals, after which he spent two years as a postdoctoral researcher developing high-efficiency silicon solar cells at Ecole Polytechnique Fédérale de Lausanne in Switzerland. His research group at ASU focuses on new materials, processes, and device designs for high-efficiency silicon solar cells and silicon-based tandem solar cells. He has been named a Moore Inventor Fellow, Trustees of ASU Professor, Fulton Entrepreneurial Professor, and Joseph C. Palais Distinguished Faculty Scholar. He is the co-founder of two solar start-up companies (Sunflex Solar and Beyond Silicon) and an advanced materials start-up company (Swift Coat).

Education
  • Ph.D. Mechanical Engineering, University of Minnesota 2010
  • B.A. Physics, Reed College 2005
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Darcy Renfro

VP External Relations, Community, Government & Economic Development

Maricopa County Community College District

Darcy Renfro is Vice Chancellor of Community, Government Relations, & Economic Development for the Maricopa County Community College District (MCCCD). She oversees workforce and economic development strategies for MCCCD and advises the Chancellor on government and community affairs. MCCCD is one of the largest community college systems in the nation serving approximately 200,000 students and nearly 10,000 faculty and staff members across 10 colleges in the metropolitan Phoenix area. As part of the Chancellor’s executive team, Ms. Renfro is helping to lead the Maricopa Transformation to fundamentally transform the student experience to meet the education and employment needs of the community.

Prior to her current role, Ms. Renfro served as the policy advisor to Governor Janet Napolitano for workforce, economic development, and higher education, and was founding Director of The Arizona We Want Institute at the Center for the Future of Arizona where she was responsible for strategic direction and development of a series of “Progress Meters” to establish clear metrics for Arizona in achieving its citizens’ goals. She previously worked as the founding Director of the Arizona STEM Education Network at Science Foundation Arizona.

Ms. Renfro is a licensed attorney in Arizona and has practiced at the Phoenix offices of Fennemore Craig, P.C. Prior to law school, she worked on Capitol Hill for U.S. Senators Dennis DeConcini (AZ) and Howard Metzenbaum (OH).

Ms. Renfro is a native of Tucson and received both her undergraduate and Juris Doctor Degrees from the University of Arizona.

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HETEROGENEOUS INTEGRATION THROUGH ADVANCED PACKAGING

  • 08:30 – 09:00

Keynote

Advanced Packaging Ecosystem

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. This trend is set to continue as on-package heterogeneous integration of diverse IP from multiple process nodes and multiple foundries will enable new product concepts, decrease time to market and deliver cost/yield benefits. Additionally, novel 3D architectures and continued die-to-die interconnect scaling are opening previously un-achievable concepts for die partitioning and on-package capability integration. These technical challenges are requiring solutions across the ecosystem (Die/Package/Board/System) which provide opportunities for groundbreaking innovation. This presentation will highlight some of the key challenges the industry will have to jointly address to enable the 3D heterogeneous integration future, such as drivers in interconnect scaling, advanced substrate developments, and technologies to enable power and performance gains. A specific example of this is optical on-package integration, where Intel is taking an aggressive approach to enable highly scalable and manufacturable solutions with applicability beyond niche designs.

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Dr. Babak Sabi

SVP & GM Assembly and Test Technology Development

Intel

Dr. Babak Sabi is a Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development.

Babak joined Intel in 1984. Prior to leading ATTD, he oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices.

Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.

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Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.

To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

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Intel
  • 09:00 – 09:30

Keynote

Unleash Product Innovations with 3DFabric

With the development of 3DIC and associated packaging technologies, semiconductor industry has extended performance and density optimization to system level, complementary to traditional chip scaling. Amid broader adoption of TSMC’s advanced 2.5D/ 3D packaging solutions along with growing chiplet complexity and form factor, the interaction between Si, packaging and components become increasingly crucial and requires continue innovations on design, process development and manufacturing.

With 3DFabric Alliance, we are extending OIP collaboration to packaging/ testing and working with industry partners on substrate and memory technology development for integrated system-level design solution to customers, together with the ecosystem of OSATs, material and equipment suppliers. In parallel, we also establish the worldwide first fully automated factory to offer best flexibility for our customers to optimize their packaging solution with better cycle time and quality control.

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Dr. Jun He photo

Dr. Jun He

VP Quality & Reliability, Advanced Packaging Technology & Service

TSMC

Dr. Jun He is Vice President of Quality & Reliability as well as Advanced Packaging Technology & Service at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). His responsibility spans across TSMC foundry eco-system and the Company’s backend business and operations management. Within the Q&R scope, his function covers incoming materials qualification, reliability and certification of new process technology & design IP, manufacturing quality as well as enabling customers for their product qualification and ramp. Besides overseeing all TSMC advanced packaging and testing manufacturing, his backend team is also accountable for key building blocks including bump/passivation/RDL process innovations and test technology development. Seamless collaboration and joint development with external partners across material, OSAT and substrate supply chain is one of his focus areas to enable customers’ product innovations at system level.

Prior to joining TSMC, Dr. He was a senior director at Intel Corporation, leading overall quality and reliability of process technology development and manufacturing. His scope included research & development of Si, advanced packaging and test along with Intel worldwide manufacturing operations.

Dr. He holds over 40 patents globally and published 50 papers in international conferences and peer-reviewed technical journals. He received his B.S. degree in Physics and Ph.D. in Materials Science from University of California, Santa Barbara.

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TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 281 distinct process technologies and manufactured 11,617 products for 510 customers in 2020 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 3-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan.

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TSMC
  • 09:30 – 10:30

Networking Break & Business Meetings 1+2

  • 10:30 – 11:00

Advanced Packaging: Enabling Moore’s Law’s Next Frontier

Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.

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Dr. Raja Swaminathan photo

Dr. Raja Swaminathan

CVP, Advanced Packaging

AMD

Dr. Raja Swaminathan is CVP, Advanced Packaging instrumental in the development of AMD’s industry leading advanced packaging roadmap. Raja has been a leader in silicon-package-system architecture definition and a co-design expert with extensive experience introducing new technologies and innovation across the silicon-packaging spectrum at Intel, Apple and AMD. He’s helped enable PPAC (power, performance, area, and cost) improvements as well as introduction of novel heterogeneous architectures throughout his career: EMIB, Apple’s Mx package architectures, 3D V-Cache, Elevated Fan-Out Bridge, High Performance Fanout to name a few. Raja received his Bachelors’ from IIT Madras and PhD from Carnegie Mellon University and has over 40 US patents in the field. He is an IEEE Senior Member and is on the technical advisory board for the Semiconductor research corporation (SRC) and Deca Technologies.

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For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.

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AMD
  • 11:00 – 11:10

Processing Innovations to Address the Manufacturing Challenges of Heterogeneous Integration

Heterogeneous design and integration has been referred to as the fourth stage in the evolution of Moore’s Law, as it enables us to integrate sets of chiplets into high performance computing packages with simultaneous improvements in power, performance, and area-cost. The need for high bandwidth and power-efficient interconnects between chiplets is driving new process technologies and automation technologies that address the higher feature densities and higher sensitivity to defects.

Large form factor panel-level processing enables higher manufacturing productivity at low cost but introduces several manufacturing challenges. The higher density of interconnections requires fine line capability that presents a challenge to traditional process equipment. Warping of the large and flexible substrates presents challenges both for handling the panels as well as the formation of reliable interconnects. The complexity of assembling multi-chiplet packages requires new factory automation solutions that can maximize product quality and factory utilization.

High resolution patterning can be achieved with materials and technologies from traditional front end processing, including PVD, Dry Etch, CVD and ALD. With its broad portfolio of semiconductor and display fabrication technologies and products, Applied Materials is addressing the challenge of delivering Front End manufacturing capability at Back End cost requirements. This presentation will highlight Applied innovations that enable panel level packaging and the factory of the future.

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Len Tedeschi

VP & GM Core Packaging Products

Applied Materials

Len Tedeschi is vice president and general manager, Core Packaging Products at Applied Materials. Len is directly responsible for the Metals Packaging Products (MPP), Packaging Plating & Cleans (PPC), Tango & Plasma Dicing product groups. His focus is ensuring customers are successful with their current products, while simultaneously solving customer’s future high value problems.

Len has worked at Applied for >20 years and has over 27 years of semiconductor experience in roles ranging from product development & support, productivity, technical strategy, marketing, and general management. Len has worked with a variety of products and technologies including etch, deposition, lithography, metrology, and inspection.

Prior to joining Packaging, Len spent 14 years in Applied’s Etch Business Unit in a wide variety of customer focused positions. Len has >10 patents granted, mainly as the lead author.

Len began his career in 1995 as a lithography equipment engineer at IDT in Santa Clara, California.

He earned a bachelor of science degree in industrial technology from San Jose State University in 1995, where he served as captain of the university’s judo team, winning two collegiate national titles, and competing in the 1996 Olympic Judo Trials.

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We are the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations Make Possible® a Better Future.

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Applied Materials
  • 11:10 – 11:30

Bridging Front End, Packaging And Substrates To Advance The Semiconductor Roadmap

For over 50 years, Moore’s Law has defined the pace of the semiconductor industry with its ability to scale transistor density every 2 years. While the front end roadmap is still progressing thanks to EUV lithography and other process technology innovations, it’s no longer sufficient to keep pace with the diversified demand of the new digital society.

In recent years, we have seen an acceleration of technical innovations in IC packaging and IC substrates to complement front end wafer fabrication technologies and meet performance, power, and cost requirements.

The implementation of heterogeneous integration started long ago with the first multi-chip modules and 2D packages and is now accelerating with several new 2.5 and 3D architectures serving various end-applications, including high-performance computing, mobile, and networking, among others.

With interconnect geometry scaling, we see the need and the opportunity to bridge process equipment and process control methodologies across the three worlds of front-end, packaging and substrates. These once completely separated domains are becoming integrated just like the packages and systems they create.

The adoption of front end-like technologies and methodologies into packaging and IC substrates is not trivial and it requires innovation and customization to meet cost and performance requirements.

KLA is partnering with key industry players to bridge these three worlds and this presentation will show the challenges we are facing and problems we are solving to advance the semiconductor technology roadmap.

Keywords: Innovation, Advanced Packaging, Technology Roadmap, Heterogeneous Integration, Substrates

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Oreste Donzella photo

Oreste Donzella

Executive VP – EPC (Electronics, Packaging, and Component) Group

KLA

Oreste Donzella serves as Executive Vice President of the Electronics, Packaging and Component (EPC) business group at KLA Corporation, which include multiple product divisions, targeting growth opportunities in specialty semiconductors, packaging, printed circuit board and display markets.

Previously, Oreste covered wide range of positions at KLA, including Chief Marketing Officer (CMO), Customer Engagement VP, General Managers of the Surfscan and SWIFT product divisions and various other technical and business roles. of KLA.

Oreste brings ~30 years of experience in the semiconductor industry. Prior to joining KLA in 1999, he spent more than six years at Texas Instruments and Micron Technology, holding engineering and management positions in the process integration and yield enhancement departments.

Oreste earned his master’s degree in electrical engineering from the University La Sapienza in Rome, Italy.

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KLA develops industry-leading equipment and services that enable innovation throughout the electronics industry. We provide advanced process control and process-enabling solutions for manufacturing wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. In close collaboration with leading customers across the globe, our expert teams of physicists, engineers, data scientists and problem-solvers design solutions that move the world forward. Additional information may be found at kla.com

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KLA
  • 11:30 – 12:45

Buffet Lunch

  • 12:45 – 13:25

IC Packaging Panel Discussion

Moderator
Curtis Zwenger photo

Curtis Zwenger

VP, Advanced SiP Product Development

Amkor Technology, Inc.

Amkor Technology, Inc.

Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and Wafer Level packaging technologies. He is currently responsible for Advanced System in Package product development. Curtis has authored numerous technical articles and papers, and he currently serves on the IMAPS Executive Council as Director of Membership. Curtis has been issued 35 US patents and holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix.

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As one of the world’s largest providers of high-quality semiconductor packaging and test services, Amkor has helped define and advance the technology landscape.

We deliver innovative solutions and believe in partnering with our customers to bring 5G, AI, Automotive, Communications, Computing, Consumer, IoT, Industrial and Networking products to market.

As a truly global supplier, Amkor has manufacturing and test capabilities as well as product development and support offices in Asia, Europe and the US.

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Panelist
Ahmer Syed photo

Ahmer Syed

VP Package Engineering

Qualcomm

Qualcomm

Ahmer Syed is a VP of Engineering at Qualcomm in Global Manufacturing Technology and Operations organization. He leads a global team responsible for packaging technology development, NPI, HVM deployment for 5G, mobile, IoT, Connectivity, Automotive, and Compute markets.

A 30+ years veteran of Semiconductor and electronics industry, Ahmer has extensive experience in developing advanced packaging technologies such as Flip Chip, WLCSP, FO-WLP, Package on Package (PoP), QFN, and System in Package (SiP). He has authored and contributed to more than 70 technical papers and articles on advanced packaging and reliability and has been a keynote speaker in various international conferences.

 

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Qualcomm is the world’s leading wireless technology innovator and the driving force behind the development, launch, and expansion of 5G. When we connected the phone to the internet, the mobile revolution was born. Today, our foundational technologies enable the mobile ecosystem and are found in every 3G, 4G and 5G smartphone. We bring the benefits of mobile to new industries, including automotive, the internet of things, and computing, and are leading the way to a world where everything and everyone can communicate and interact seamlessly.

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Panelist
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Tony LoBianco

Head of Global Packaging

Skyworks Solutions

Skyworks Solutions

Tony is Sr Director of Global Packaging for Skyworks Solutions. His teams lead advanced packaging R&D and production for wireless semiconductor products, including cellular, infrastructure, automotive, defense, IoT, and others.

He holds degrees in Chemical Engineering from the University of Illinois Champaign-Urbana and an MBA in Technology Management.

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Skyworks Solutions, Inc. is empowering the wireless networking revolution. Our highly innovative analog semiconductors are connecting people, places and things spanning a number of new and previously unimagined applications within the aerospace, automotive, broadband, cellular infrastructure, connected home, entertainment and gaming, industrial, medical, military, smartphone, tablet and wearable markets.

Skyworks is a global company with engineering, marketing, operations, sales and support facilities located throughout Asia, Europe and North America and is a member of the S&P 500® and Nasdaq-100® market indices (Nasdaq: SWKS).

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Panelist
Deepak Kulkarni photo

Deepak Kulkarni

Senior Fellow Advanced Packaging

AMD

AMD

Deepak Kulkarni is a Fellow, Advanced Packaging at AMD. Deepak has over 15 years of experience in packaging technology development. Over the years, he has held several leadership positions driving substrate technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds 17 patents and nineteen publications on various aspects of packaging such as 2.5D/3D architectures, DFM/DFY and AI techniques applied to yield management. His contributions to the semiconductor industry have been recognized by an Intel Achievement Award, Next 5% award (AMD) and best paper award (ITHERM). Deepak holds a PhD from the University of Illinois Urbana-Champaign with a major in mechanical engineering and a minor in computational science.

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For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.

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Panelist
Rahul Manepalli, Ph.D. photo

Rahul Manepalli, Ph.D.

Intel Fellow; Director Substrate TD Module Engineering

Intel

Intel

Rahul Manepalli is an Intel Fellow and Sr. Director of Module Engineering in the Substrate Package Technology Development Organization in Intel. Rahul and his team are responsible for developing next generation of materials, processes and equipment for Intel’s package pathfinding and development efforts. His team has been the driving force behind many of the technology innovations in Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and other substrate technologies. Rahul has also had an instrumental role in leading Intel’s assembly materials development and pathfinding efforts leading to several innovations in encapsulants, thermal interface materials and solder alloys. Rahul is the author of over 100 patent publications in semiconductor packaging, over 50 technical papers and invited talks and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.

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Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.

To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

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  • 13:25 – 13:55

A 360 View of Semiconductor Test from AI and Security Perspective

This keynote will explore the impact of deep learning including large language models on the semiconductor test. We will highlight the opportunities these models present for real-time data processing and discovery of insights, with specific applications in computer vision and natural language processing. However, the use of these models also introduces new security risks, particularly regarding the use of cloud infrastructure for collection of data, training and inference. By examining past attacks on networks, we will discuss the potential for malicious actors to steal data or intellectual property from companies. Attendees will gain an understanding of the opportunities and challenges in AI and security for the coming years and the importance of considering security measures in the development and deployment of these advanced solutions.

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Claudionor Coelho

Chief AI Officer, SVP of Engineering

Advantest

Claudionor N. Coelho is the Chief Artificial Intelligence Officer and SVP of Engineering at Advantest, being responsible for AI strategy for Advantest and leading engineering for ACS.

Previously, he was the VP/Fellow for AI – Head of AI Labs at Palo Alto Networks, where he led AI and Neurosymbolic innovation for AIOps products at Palo Alto Networks. He also led the creation of next-generation time series analysis tools at scale (MLOps on GCP) integrated with knowledge graphs and formal technology.

He worked on Machine Learning/Deep Learning at Google. He is the creator of QKeras, a Deep Learning package for quantization on top of Keras with support for automatic quantization, being used by CERN (which made it to the cover page of Nature Machine Intelligence in August 2021). He was the VP of Software Engineering, Machine Learning, and Deep Learning at NVXL Technology. He did seminal work on AI at Synopsys Inc, and he opened the site for Cadence Design Systems in Brazil, being the GM for the site, following the acquisition of Jasper Design Automation, where he was the Worldwide SVP of R&D. Under his leadership, Jasper was awarded one of the most innovative companies in the US in 2013, according to Red Herring.

He created the initial strategy for Kunumi (when he was an angel investor), and he is an investor and is on the TAB of ConDati. He has more than 100 papers, patents, academic, and industry awards. He is currently an Invited Professor for Deep Learning at Santa Clara University, and previously, he was an Associate Professor of Computer Science at UFMG, Brazil, when he took the ACM Programming Contest to the Southern Hemisphere. He has a Ph.D. in EE/CS from Stanford University, an MBA from IBMEC Business School, and an MSCS and BSEE (summa cum laude) from UFMG, Brazil.

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Advantest (TSE: 6857) is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors for applications including 5G communications, the Internet of Things (IoT), autonomous vehicles, artificial intelligence (AI), machine learning, smart medical devices and more. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also conducts R&D to address emerging testing challenges and applications, produces multi-vision metrology scanning electron microscopes essential to photomask manufacturing, and offers groundbreaking 3D imaging and analysis tools. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and an international commitment to sustainable practices and social responsibility. More information is available at www.advantest.com.

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Advantest
  • 13:55 – 14:25

Package Design and Reliability Need in Server Systems

As power consumption in data-centers assumes increased importance, the role packaging and package reliability plays assumes a critical role. In this presentation we will review key trends in the server market, review various package technologies, modeling techniques as well as some innovative power solutions that are being implemented in servers.

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Viresh Patel

VP Packaging Technology

Renesas

  • Vice President of Advance Packaging Technology and Assembly Engineering Operations & Managing all IoT and Infrastructure (IIBU) support (~ $7B Rev) for Renesas World Wide.
  • 35 Years in Semiconductor Industry
  • Prior to being at Renesas, part of the Acquisition of IDT by Renesas(VP , Sr. Dir, Dir) , Maxim (now ADI), Cirrus Logic, and Allegro Microsystem.
  • Hold BS in Mechanical Engineering & Mathematics from University of Massachusetts , Amherst.
  • Hold More than 15 USA and International issued Patents, and have published several articles in Advance Packaging and Thermal management of Semiconductors.
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Renesas Electronics empowers a safer, smarter and more sustainable future where technology helps make our lives easier.

A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live.

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Renesas
  • 14:25 – 15:25

Networking Break & Business Meetings 3+4

SEMICONDUCTOR MARKET OUTLOOK

  • 15:25 – 15:55

Navigating Through a Correction in the Semiconductor Market

  • What are IDC’s expectations for revenue growth this year and 2024? Year over year growth is expected to resume by Q4’23 but the total semiconductor market is expected to decline in high single digits.
  • Current State of the market: Market correction is well underway and will continue throughout this year on a revenue and unit basis. The worst of the storm for our industry is expected to be from Q3’22 to Q2’23.
    Inventory correction began in 1H’22, accelerated by the second half and will continue for the next couple of quarters driving down utilization rates and revenues.
  • DRAM and NAND is experiencing a prolonged contraction. How are suppliers adjusting to the large inventory and bit growth decline? Will Samsung cutback like the other suppliers to balance the market?
  • Our forecast scenario factors a moderate global recession that begins in Q4’22/Q1’23 (4-6 quarters). Eurozone is assumed to already be in recession and China remains weak for most of this year. Capital spending cutbacks reach 20% for the industry with higher percentage cutbacks and pushouts in memory. Logic will also reevaluate capacity expansion plans as utilization falls and projects are reevaluated.
  • Long term IDC believes the market will grow at a CAGR of 5% over the next 5 to 7 years with automotive and industrial outperforming the overall industry with increasing silicon content. Technology spending as a percentage of GDP remains less than 1% but should more than triple over the next seven years. We expect 2024 and 2025 will be a strong recovery period for semiconductors but WFE likely remains down in 2024 after a strong three-year cycle.
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Mario Morales

Group VP, Enabling Technologies and Semiconductors

IDC

Mario Morales is the group vice president of IDC’s enabling technologies, semiconductor, storage, and DataSphere research.

He is responsible for in-depth analysis, evaluation of emerging markets and trends, forecasting, and research of major semiconductor industry segments such as embedded and intelligent systems, wireless, personal computing, networking and cloud infrastructure, automotive electronics, and AI semiconductors.

BACKGROUND

Mr. Morales is an accomplished program vice president, manager, and industry expert with over 25 years of experience in building a multinational top-tier consulting, sales, and research team and driving a set of established businesses. Solid experience in managing strategic partnerships and advisory services with IDC’s largest multinational clients. Strong analytical, strategic planning skills, and managing complex projects involving strong collaboration across geographies, functional groups, and business units. Proven leadership skills and instrumental at establishing research and business KPIs.

Mr. Morales is a trusted advisor to leading high tech company executives, financial investors, and bankers on market landscape and direction, product and technology positioning, competitive benchmarking, M&A, HW, and SW technology, and brand health and sustainability. Established relationships with technology suppliers including Intel, Samsung, TSMC, Qualcomm, Huawei, HP, AMD, NVIDIA, Microsoft, Facebook, TI, Micron, UMC, SoftBank, ARM, NXP, and others.

Mr. Morales is the leading advisor and expert analyst for IDC’s largest Wall Street clients including investment banking, VC’s, and mutual and hedge funds across every major financial region.

Over his career, Mr. Morales has authored and co-authored over 240 reports and studies in the area of semiconductors, mobile, PC, wireless, embedded, IoT, and IT marketplace. His team is responsible for some of the most interesting and evolving tech in our industry including coverage of microprocessors, accelerated computing, storage, memory, sensors and connectivity. His team has been responsible for initiating coverage of emerging technologies for IDC, and driving new research business practices, and creating leading industry market models in DRAM, NAND, Embedded processors and controllers, AI ML architectures, cellular baseband modems, WiFi, cellular broadband, digital consumer, foundry, EMS, and intelligent systems.

His career includes past positions with NEC Electronics and Dataquest.

EDUCATIONAL ACCOMPLISHMENTS

  • B.S. in Finance and Accounting from San Jose State University
  • Fluent in English and Spanish
  • Frequent presenter and advisor to CEOs and executive teams across his portfolio of clients
  • Strong reputation as an advisor and industry expert on Wall Street
  • IDC executive analyst for Intel and Qualcomm
  • Frequent speaker, presenter, and moderator at IDC Directions events in Asia and semiconductor industy conferences including ISS, GSA, CASPA, CISES, and SEMI
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IDC is the premier global provider of market intelligence, advisory services, and events for the information technology, telecommunications, and consumer technology markets. IDC helps IT professionals, business executives, and the investment community make fact-based decisions on technology purchases and business strategy. More than 1,100 IDC analysts provide global, regional, and local expertise on technology and industry opportunities and trends in over 110 countries worldwide. For more than 50 years IDC has provided strategic insights to help our clients achieve their key business objectives. IDC’s Insights businesses provide industry-focused advice for IT buyers in the Financial, Government, Health, Retail, Manufacturing and Energy verticals. IDC is a subsidiary of IDG, the world’s leading technology media, research, and events company. You can learn more about IDC by visiting www.idc.com.

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IDC

EQUIPMENT SUPPLIER SESSION

  • 15:55 – 16:05

Not All Nanograined Copper Is Created Equal

Previously we have demonstrated that electroplated copper could be engineered to have microstructures at um and nm scales. This paper shows that not all nanograined copper is created equal. Through systematic investigations, significant insight is obtained into the necessary conditions to create a stable nanograined copper that meets the following criteria: 1. microstructure stable over 9 months at ambient storage conditions, 2. textures of the electrodeposited copper do not depend on substrate types and their textures, 3. grain growth increases to micron scale at temperatures above 150 C. Furthermore, we shall introduce a concept of nanograin threshold in the context of RT microstructure stability.

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Dr. Yun Zhang photo

Dr. Yun Zhang

Founder & CEO

Shinhao Materials

Dr Yun Zhang, founder and CEO of Shinhao Materials LLC, has been active in materials innovation, R&D, marketing and sales for over 28 years, holding 34 granted patents, and numerous peer-reviewed journal publications and awards. She started her career at AT&T Bell labs in 1994, carrying out materials research and development. Her work on tin whisker growth won international recognition for demonstrating experimentally for the first time its driving force and for developing mitigation solutions. In 2002, she was appointed global R&D director by Cookson Electronics Enthone for its electronics business. In the subsequent 10 years, her insight and leadership in fundamental understanding of electrodeposition process at a molecule level, combined with a deep appreciation of technology trends and customer needs has won Dr. Zhang many friends and willing partners at top tier equipment manufacturers and key customers. Those close and collaborative partnerships resulted in win-win to all parties for RDL, copper pillar and TSV plating. She received a BS in chemistry from Nanjing University, and a PhD in chemistry from Brown University.

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Shinhao Materials LLC is located in Suzhou China. Its mission is to invent and produce new materials to meet the ever-changing needs of the semiconductor industry, to service its customers in timely and cost-effective way. Being technology heavy, asset light, it has focused on technology innovation. Through its relatively short life, it has developed several unique classes of copper plating additives that have shown to be effective in addressing electrical, thermal, and stress challenges we are facing today. Its IntraCu® products are patent-protected in US, Korea, Taiwan and mainland China. In 2019, Shinhao Materials formed a strategic partnership with Umicore EP to sell and service its customers better internationally.

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Shinhao Materials

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