08:00 – 08:10

Welcome Speech

Salah Nasri

CEO & Co-Founder

I.S.E.S.

08:10 – 08:30

Greater Phoenix: A Global Destination for Industrial Innovation

Greater Phoenix is home to an ever-expanding ecosystem of semiconductor manufacturing and its supply chain. Long-term strategic planning of resources at the state and regional level have supported this growth, ensuring that adequate water and nation-leading grid reliability meet the needs of industry. Paired with a robust workforce and an educational system anchored by Arizona State University and the Maricopa County Community College District, the region has the requisite labor force to meet the needs of key industry sectors. Greater Phoenix is a top global destination for businesses and uniquely positioned to seize the momentum of technological innovation and advanced industry to support future development.

Chris Camacho photo

Chris Camacho

President & CEO

Greater Phoenix Economic Council (GPEC)

Zachary Holman photo

Zachary Holman, Ph.D.

Associate Professor and Director of Faculty Entrepreneurship

Arizona State University

Darcy Renfro photo

Darcy Renfro

VP External Relations, Community, Government & Economic Development

Maricopa County Community College District

Darcy Renfro photo

Darcy Renfro

VP External Relations, Community, Government & Economic Development

Maricopa County Community College District

HETEROGENEOUS INTEGRATION THROUGH ADVANCED PACKAGING

08:30 – 09:00

Keynote

Advanced Packaging Ecosystem

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. This trend is set to continue as on-package heterogeneous integration of diverse IP from multiple process nodes and multiple foundries will enable new product concepts, decrease time to market and deliver cost/yield benefits. Additionally, novel 3D architectures and continued die-to-die interconnect scaling are opening previously un-achievable concepts for die partitioning and on-package capability integration. These technical challenges are requiring solutions across the ecosystem (Die/Package/Board/System) which provide opportunities for groundbreaking innovation. This presentation will highlight some of the key challenges the industry will have to jointly address to enable the 3D heterogeneous integration future, such as drivers in interconnect scaling, advanced substrate developments, and technologies to enable power and performance gains. A specific example of this is optical on-package integration, where Intel is taking an aggressive approach to enable highly scalable and manufacturable solutions with applicability beyond niche designs.

Dr. Babak Sabi photo

SVP & GM Assembly and Test Technology Development

09:00 – 09:30

Keynote

Unleash Product Innovations with 3DFabric

With the development of 3DIC and associated packaging technologies, semiconductor industry has extended performance and density optimization to system level, complementary to traditional chip scaling. Amid broader adoption of TSMC’s advanced 2.5D/ 3D packaging solutions along with growing chiplet complexity and form factor, the interaction between Si, packaging and components become increasingly crucial and requires continue innovations on design, process development and manufacturing.

With 3DFabric Alliance, we are extending OIP collaboration to packaging/ testing and working with industry partners on substrate and memory technology development for integrated system-level design solution to customers, together with the ecosystem of OSATs, material and equipment suppliers. In parallel, we also establish the worldwide first fully automated factory to offer best flexibility for our customers to optimize their packaging solution with better cycle time and quality control.

Dr. Jun He photo

Dr. Jun He

VP Quality & Reliability, Advanced Packaging Technology & Service

TSMC

09:30 – 10:30

Networking Break & Business Meetings 1+2

10:30 – 11:00

Advanced Packaging: Enabling Moore’s Law’s Next Frontier

Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.

Raja Swaminathan, Ph.D.

CVP, Advanced Packaging

AMD

11:00 – 11:10

Processing Innovations to Address the Manufacturing Challenges of Heterogeneous Integration

Heterogeneous design and integration has been referred to as the fourth stage in the evolution of Moore’s Law, as it enables us to integrate sets of chiplets into high performance computing packages with simultaneous improvements in power, performance, and area-cost. The need for high bandwidth and power-efficient interconnects between chiplets is driving new process technologies and automation technologies that address the higher feature densities and higher sensitivity to defects.

Large form factor panel-level processing enables higher manufacturing productivity at low cost but introduces several manufacturing challenges. The higher density of interconnections requires fine line capability that presents a challenge to traditional process equipment. Warping of the large and flexible substrates presents challenges both for handling the panels as well as the formation of reliable interconnects. The complexity of assembling multi-chiplet packages requires new factory automation solutions that can maximize product quality and factory utilization.

High resolution patterning can be achieved with materials and technologies from traditional front end processing, including PVD, Dry Etch, CVD and ALD. With its broad portfolio of semiconductor and display fabrication technologies and products, Applied Materials is addressing the challenge of delivering Front End manufacturing capability at Back End cost requirements. This presentation will highlight Applied innovations that enable panel level packaging and the factory of the future.

Len Tedeschi photo

Len Tedeschi

VP & GM Core Packaging Products

Applied Materials

11:10 – 11:30

Bridging Front End, Packaging And Substrates To Advance The Semiconductor Roadmap

For over 50 years, Moore’s Law has defined the pace of the semiconductor industry with its ability to scale transistor density every 2 years. While the front end roadmap is still progressing thanks to EUV lithography and other process technology innovations, it’s no longer sufficient to keep pace with the diversified demand of the new digital society.

In recent years, we have seen an acceleration of technical innovations in IC packaging and IC substrates to complement front end wafer fabrication technologies and meet performance, power, and cost requirements.

The implementation of heterogeneous integration started long ago with the first multi-chip modules and 2D packages and is now accelerating with several new 2.5 and 3D architectures serving various end-applications, including high-performance computing, mobile, and networking, among others.

With interconnect geometry scaling, we see the need and the opportunity to bridge process equipment and process control methodologies across the three worlds of front-end, packaging and substrates. These once completely separated domains are becoming integrated just like the packages and systems they create.

The adoption of front end-like technologies and methodologies into packaging and IC substrates is not trivial and it requires innovation and customization to meet cost and performance requirements.

KLA is partnering with key industry players to bridge these three worlds and this presentation will show the challenges we are facing and problems we are solving to advance the semiconductor technology roadmap.

Keywords: Innovation, Advanced Packaging, Technology Roadmap, Heterogeneous Integration, Substrates

Oreste Donzella photo

Oreste Donzella

Executive Vice President and Chief Strategy Officer

KLA

11:30 – 12:45

Buffet Lunch

12:45 – 13:25

IC Packaging Panel Discussion

Curtis Zwenger photo

Moderator

Curtis Zwenger

Ahmer Syed photo

Panelist

Ahmer Syed

VP Package Engineering

Qualcomm Technologies Inc.

Tony LoBianco photo

Panelist

Tony LoBianco

Head of Global Packaging

Skyworks Solutions

Deepak Kulkarni photo

Panelist

Deepak Kulkarni

Senior Fellow Advanced Packaging

AMD

Rahul Manepalli, Ph.D. photo

Panelist

Rahul Manepalli, Ph.D.
Intel Fellow; Director Substrate TD Module Engineering

Intel Corporation

13:25 – 13:55

A 360 View of Semiconductor Test from AI and Security Perspective

This keynote will explore the impact of deep learning including large language models on the semiconductor test. We will highlight the opportunities these models present for real-time data processing and discovery of insights, with specific applications in computer vision and natural language processing. However, the use of these models also introduces new security risks, particularly regarding the use of cloud infrastructure for collection of data, training and inference. By examining past attacks on networks, we will discuss the potential for malicious actors to steal data or intellectual property from companies. Attendees will gain an understanding of the opportunities and challenges in AI and security for the coming years and the importance of considering security measures in the development and deployment of these advanced solutions.

Claudionor Coelho photo

Claudionor Coelho

Chief AI Officer, SVP of Engineering

Advantest

13:55 – 14:25

Package Design and Reliability Need in Server Systems

As power consumption in data-centers assumes increased importance, the role packaging and package reliability plays assumes a critical role. In this presentation we will review key trends in the server market, review various package technologies, modeling techniques as well as some innovative power solutions that are being implemented in servers.

Viresh Patel photo

Viresh Patel

VP Packaging Technology

Renesas Electronics

14:25 – 15:25

Networking Break & Business Meetings 3+4

SEMICONDUCTOR MARKET OUTLOOK

15:25 – 15:55

Navigating Through a Correction in the Semiconductor Market

  • What are IDC’s expectations for revenue growth this year and 2024? Year over year growth is expected to resume by Q4’23 but the total semiconductor market is expected to decline in high single digits.
  • Current State of the market: Market correction is well underway and will continue throughout this year on a revenue and unit basis. The worst of the storm for our industry is expected to be from Q3’22 to Q2’23.
    Inventory correction began in 1H’22, accelerated by the second half and will continue for the next couple of quarters driving down utilization rates and revenues.
  • DRAM and NAND is experiencing a prolonged contraction. How are suppliers adjusting to the large inventory and bit growth decline? Will Samsung cutback like the other suppliers to balance the market?
  • Our forecast scenario factors a moderate global recession that begins in Q4’22/Q1’23 (4-6 quarters). Eurozone is assumed to already be in recession and China remains weak for most of this year. Capital spending cutbacks reach 20% for the industry with higher percentage cutbacks and pushouts in memory. Logic will also reevaluate capacity expansion plans as utilization falls and projects are reevaluated.
  • Long term IDC believes the market will grow at a CAGR of 5% over the next 5 to 7 years with automotive and industrial outperforming the overall industry with increasing silicon content. Technology spending as a percentage of GDP remains less than 1% but should more than triple over the next seven years. We expect 2024 and 2025 will be a strong recovery period for semiconductors but WFE likely remains down in 2024 after a strong three-year cycle.
Mario Morales photo

Mario Morales

Group VP, Enabling Technologies and Semiconductors

IDC

EQUIPMENT SUPPLIER SESSION

15:55 – 16:05

Not All Nanograined Copper Is Created Equal

Previously we have demonstrated that electroplated copper could be engineered to have microstructures at um and nm scales. This paper shows that not all nanograined copper is created equal. Through systematic investigations, significant insight is obtained into the necessary conditions to create a stable nanograined copper that meets the following criteria: 1. microstructure stable over 9 months at ambient storage conditions, 2. textures of the electrodeposited copper do not depend on substrate types and their textures, 3. grain growth increases to micron scale at temperatures above 150 C. Furthermore, we shall introduce a concept of nanograin threshold in the context of RT microstructure stability.

Dr. Yun Zhang photo

Dr. Yun Zhang

Founder & CEO

Shinhao Materials

16:05 – 16:15

Valuation of Artificial Intelligence for Semiconductor Equipment

Applications for Artificial Intelligence (AI) have grown substantially over the last few years in the legal, medical, and automotive industries. These business sectors are regulated more heavily than semiconductor manufacturing equipment is, but use of AI in the semiconductor industry is lagging. The costs and benefits of AI are relatively easy to project, so it follows that AI has been studied and found that large-scale adoption provides an insufficient return on investment. A cost model will be proposed showing likely AI growth areas such as automated maintenance tasks and performance benchmarking, and a few that may remain out of reach.

Jon Hander photo

Jon Hander

AVP Panel Products

ASMPT Limited

16:15 – 16:25

Advanced Packaging Materials and Evaluation Platform at Resonac

Resonac has started Packaging Solution Center as new R&D center to propose one-stop solution for customers in 2018 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package in October, 2021.

2.xD and 3D packages require to connect chips and components in high density, therefore, both wiring pitch and vertical interconnect dimension must be finer and finer. At the same time, in order to achieve better performance, more and more chips are integrated together and thus the package size is increasing. To meet these requirement, we are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large 2.5D advanced package.

The presentation will cover the significance and strengths of JOINT2, and updates on research and development.

Hidenori Abe

CTO, Semiconductor Materials, Resonac Holdings Corporation

Resonac Corporation

16:25 – 16:30

AICS Solutions to High Value Problems

The “More than Moore” era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75 mm x 75 mm to 175 mm x 175 mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges for advanced IC substrates. The large package size reduces the number of units per panel, making the panel yield of paramount importance. In addition, with the increasing number of RDL layers, alignment shift per buildup step, due to the process induced substrate distortion can lead to a steady overlay drift and increase the RDL total interconnect length to a point where it exceeds the resistance specification. Solutions to these high value problems will be the subject of this talk.

Keith Best photo

Keith Best

Director, Product Marketing, Lithography

Onto Innovation

16:35 – 16:45

Advanced Packaging – the Need for Standards

Dr. Shekhar Chandrashekhar photo

Dr. Shekhar Chandrashekhar

CEO

iNEMI

16:45 – 17:30

Workforce Diversity Initiatives in the CHIPS Act Panel Session

Amy Leong photo

Moderator

Amy Leong

Chief Marketing Officer and Senior Vice President, Mergers and Acquisitions

FormFactor

Ann Kelleher photo

Panelist

Dr. Ann Kelleher

EVP & GM Technology Development

Intel Corporation

Najwa Khazal photo

Panelist

Najwa Khazal

General Manager STC Americas

Christine Dunbar photo

Panelist

Christine Dunbar

SVP Global Sales

Robin Davis photo

Panelist

Robin Davis
Director Business Development

Deca Technologies

18:00 – 19:00

Cocktail Reception Sponsored by Green Technology Investments LLC (GTI)

Tal Levin photo

Tal Levin

Executive Vice President

GTI (Green Technology Investments)

19:00 – 21:00

Gala Dinner Sponsored by TEL

+ Industry Awards Ceremony

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Mark Dougherty

President TMEA – TEL Manufacturing and Engineering of America

Tokyo Electron

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