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ISES Advanced Packaging The Titans – Live Webinar
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Webinar Agenda
Advanced Packaging Architectures: Opportunities and Challenges
Presented by: Babak Sabi, Corporate VP, GM Assembly and Test Technology Development – Intel
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3DFabricTM for System Level Innovation
Presented by: Marvin Liao, VP Advanced Packaging and Technology Services – TSMC
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Heterogeneous Integration : Chiplet packaging technology for Next Gen. Devices
Presented by: Seungwook Yoon, Corporate VP/Head of Team of Package Technology Strategy and Planning – Samsung Electronics
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Presentations
Corporate VP, GM Assembly and Test Technology Development – Intel
Babak Sabi is the Corporate Vice President and General Manager Assembly & Test Technology Development. Since 2009, he has been responsible for the company’s packaging assembly process, packaging materials, enabling assembly and test technology development. Sabi joined Intel in 1984. Prior to leading ATTD, Sabi led the Corporate Quality Network within Intel’s Technology Manufacturing Group from 2002 to 2009. He led a company-wide network of quality and reliability organizations responsible for product reliability, customer satisfaction and quality business practices. Previously, Sabi managed technology development quality and reliability, and was responsible for silicon technology certification, assembly, test and board processes. Sabi received his Ph.D in solid state electronics from Ohio State University in 1984. He has written 10 papers on reliability physics and has received five Intel Achievement Awards. He currently hold two patents.
Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. As a result, several innovative packaging architectures have been announced in recent years. On-package integration provides a compact, power efficient platform for Heterogeneous Integration of diverse IP that support faster time to market and cost/yield benefits. In this talk, I will describe current technology envelopes and future scaling directions for representative advanced packaging architectures. Key areas of focus will be (1) interconnect scaling, (2) power efficient high bandwidth signaling including optical interconnects, (3) Hybrid Bonding, (4) test challenges for chiplets/die block assembly, and (5) advanced power delivery technologies. The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization and supply chain development.
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, in Silicon Valley. It is the world’s largest and highest-valued semiconductor chip manufacturer on the basis of revenue, and is the developer of the x86 series of microprocessors, the processors found in most personal computers. Intel ranked No. 46 in the 2018 Fortune 500 list of the largest United States corporations by total revenue. Intel is incorporated in Delaware.
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VP Advanced Packaging and Technology Services – TSMC
Education:
Ph.D., Materials Science, University of Texas at Arlington, USA, 1989
Bachelor, Materials Science, Tsing Hua University, Taiwan, 1979
Experience:
tsmc Advanced Packaging Technology and Service,2011 ~ now
tsmc Special Project, 2009 ~ 2010
tsmc Fab 6 Director, 2003 ~ 2009
Chartered Semiconductor, 1997 ~ 2002 (Singapore)
Applied Materials, 1994 ~ 1997 (USA)
SGS Thomson Microelectronics (STM), 1990 ~1994 (USA)
3DFabricTM is an integrated SoICTM frond-end chip stacking and back-end advanced packaging solution developed to meet future HPC and 5G system need.
In this solution SoICTM chip stacking technology provides cost and performance for future leading node chiplets integration. The fine pad pitch capability in SoICTM
can unleash the innovation for chiplet integration to reach highest performance. CoWoS® advanced packaging with 3 types of interposer, silicon, RDL and LSI (local silicon interconnect) offer the best 2.5D packaging solution for large size package with HBM integration, fine pitch capability, reliability, and cost.
A 3DFabricTM Intelligent Fab with AMHS automation, production traceability, big data analysis, and precision process control to achieve faultless manufacturing will be built for SoICTM production and quality need in the near future.
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the worlds largest dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
TSMC deployed 272 distinct process technologies, and manufactured 10,761 products for 499 customers in 2019 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 5-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan.
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Corporate VP/Head of Team of Package Technology Strategy and Planning, – Samsung Electronics
Dr. Yoon is currently working as Corporate VP/Head of Team of Package Technology Strategy and Planning, Samsung Electronics.
Prior to joining Samsung, He was director of group technology strategy, STATS ChipPAC, JCET Group. He also worked deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Served as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.
The best solution for optimizing silicon systems for any given new workload is to create a system on chip (SoC), monolithic chip. But this gets more expensive with demand for high-performance AI, HPC applications and advanced Si node technology. One way of reducing the cost of Silicon systems for emerging workloads would be to use chiplet technology. From a commercial standpoint, this approach makes a lot of sense. The cost of a highly integrated SoC can be very high- so high it‘s prohibitive for many. Furthermore, the complexity of such highly integrated semiconductor systems makes manufacturing more challenging: there is a direct correlation between higher complexity and yield loss. The package technology now sits in the center of the universe for the next generation of devices.
In this presentation, various chiplet packaging technologies including MCM, SiP, integrated wafer level packaging solutions such as 2.5D and 3D will be introduced. These solutions have demonstrated their unique advantages in many applications that require high-end chips (such as CPU, GPU, AI, FPGA, network) in combination with high bandwidth memory from a system/package co-design and performance.
Company profile coming soon…
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