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HPC, AI, Chiplets, heterogeneous integration
Mark Fuselier
SVP Technology & Product Engineering
AMD
CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Update
Dan Berger
Associate Director
CHIPS for America R&D Office
Glass Substrates for Advanced Packaging
Dr. Xavier Lafosse
Commercial Technology Director, Advanced Optics
Corning Incorporated
Greater Phoenix: Semiconductor Excellence on the Global Stage
Chris Camacho
President & CEO
Greater Phoenix Economic Council (GPEC)
Semiconductor Market Outlook: Investment and Innovation Accelerate Next Growth Cycle
Mario Morales
Group VP, Enabling Technologies and Semiconductors
IDC
Optimizing Interconnect Density with New Packaging Technologies
Oreste Donzella
Executive Vice President and Chief Strategy Officer
KLA
A Game-Changer for AI and HPC Substrates: A Novel Interconnect Technology
Rozalia Beica
Chief Commercial Officer
Silicon Manufacturing and Packaging at MSFT in the Cloud/AI era
Sriram Srinivasan
Partner Silicon Packaging Technology
Microsoft
Challenges to enabling the transition from organic to glass core substrates as RDL approaches 2 µm l/s and beyond
Keith Best
Director, Product Marketing, Lithography
Onto Innovation
Advanced Packaging/Substrate Materials and Open innovation Platform
Hidenori Abe
CTO, Semiconductor Materials, Resonac Holdings Corporation
Resonac Corporation
Optimizing Cost and Quality Through Test Mobility Across Insertions
Rick Burns
President Semiconductor Test Division
Teradyne
Test Challenges in the AI & Chiplet era
Srini Chinamilli
Co Founder & CEO
Tessolve
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