In the high-performance computing segment, we continue to see an explosion in demand for computing fueled by the proliferation of AI, 5G and edge computing. However, the slowing of Moore’s law has made it challenging to support this demand with traditional monolithic processors. The advent of large language models is also driving a significant demand for memory and high bandwidth interconnects between the compute and memory chips. Chiplet architecture provides a solution to meet the insatiable demand for compute and memory. By creating custom, modular chiplets and integrating heterogeneous architectures on to one package the overall performance of the processor can be enhanced. Advanced packaging technology such as 2.5D and 3D packaging provide solutions to improve the energy efficiency of the interconnects.

In this talk we will dig deeper into the compute and memory demand for AI accelerator chips. We will review AMDs latest innovations on leveraging 2.5D and 3D packaging to drive performance enhancement and energy efficiency. We delve into the design, process co-optimization needed to achieve higher performance while controlling costs and power consumption. We will conclude our talk with a summary of opportunities and challenges that lie ahead.