Advanced Packaging: Enabling Moore’s Law’s Next Frontier

ISES Docs:

Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.

Dr. Raja Swaminathan photo

Dr. Raja Swaminathan

CVP, Advanced Packaging

AMD

Members Only

Sorry ISES Docs are exclusive to ISES Members

For access please either login to your membership account or visit our Membership page to sign up for ISES membership.