How Laser is Enabling The Power Semiconductor Roadmap

ISES Docs:

To keep up with the drive for improved electrical performance of Power Semiconductor devices, chip designers are looking at thinner wafers and moving from Si to SiC and GaN wafer substrates. Due to the increased electrification in our daily life we see a strong increase in power semiconductor applications for mobile, automotive, industrial, renewable energies, etc. As a result of this increase in volume, the market is looking at new wafer singulation technologies to keep up with the technology requirements as well as the cost. ASMPT developed a patented Ultra-Violet (UV) nano second laser dicing technology for thin SiC wafers (100 – 150 μm), which allows customers to continue their technology roadmap and which is competitive from a Cost of Ownership (CoO) to the conventional saw blade dicing technology. Blade dicing is encountering yield issues and due to the hardness of SiC, high consumable cost and low throughput. During our presentation at ISES EU Power 2023 we will share the laser technology concept used and the results achieved for dicing of thin SiC power semiconductor devices including reliability data and CoO.

Key words: SiC, Dicing, Power Semiconductors, Thin Wafer, Multiple Beam

Jeroen van Borkulo photo

Jeroen van Borkulo

Head of Business & Marketing

ASMPT Limited

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