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Greater Phoenix: Semiconductor Excellence on the Global Stage

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Chris Camacho

President & CEO

Greater Phoenix Economic Council (GPEC)

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Advanced Packaging: Navigating System Technology Co-optimization & Embracing Innovation

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Dr. Ann Kelleher

EVP & GM Technology Development

Intel Corporation

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CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Update

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Dan Berger

Associate Director

CHIPS for America R&D Office

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HPC, AI, Chiplets, heterogeneous integration

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Mark Fuselier

SVP Technology & Product Engineering

AMD

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Optimizing Interconnect Density with New Packaging Technologies

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Oreste Donzella

Executive VP – EPC (Electronics, Packaging, and Component) Group

KLA

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Silicon Manufacturing and Packaging at MSFT in the Cloud/AI era

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Sriram Srinivasan

Partner Silicon Packaging Technology

Microsoft

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Optimizing Cost and Quality Through Test Mobility Across Insertions

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Rick Burns

President Semiconductor Test Division

Teradyne

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Test Challenges in the AI & Chiplet era

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Srini Chinamalli

Co Founder & CEO

Tessolve

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Challenges to enabling the transition from organic to glass core substrates as RDL approaches 2 µm l/s and beyond

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Keith Best

Director, Product Marketing, Lithography

Onto Innovation

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Co-Packaged Optics and Solutions for High Volume manufacturing

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Dr. Johann Weinhändler

Managing Director

ASMPT Limited

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Glass Substrates for Advanced Packaging

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Dr. Xavier Lafosse

Commercial Technology Director, Advanced Optics

Corning Advanced Optics

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Panel Discussion: Marking the Memory Wall a Memory: Prespectives on Technical and Economic Challenges

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Dr. Ravi Mahajan

Intel Fellow, Assembly and Packaging Technology Pathfinding

Intel Corporation

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