Members Only

Sorry ISES TV videos are exclusive to ISES Members

For access please either login to your membership account or visit our Membership page to sign up for ISES membership.


Processing Innovations to Address the Manufacturing Challenges of Heterogeneous Integration

Heterogeneous design and integration has been referred to as the fourth stage in the evolution of Moore’s Law, as it enables us to integrate sets of chiplets into high performance computing packages with simultaneous improvements in power, performance, and area-cost. The need for high bandwidth and power-efficient interconnects between chiplets is driving new process technologies and automation technologies that address the higher feature densities and higher sensitivity to defects.

Large form factor panel-level processing enables higher manufacturing productivity at low cost but introduces several manufacturing challenges. The higher density of interconnections requires fine line capability that presents a challenge to traditional process equipment. Warping of the large and flexible substrates presents challenges both for handling the panels as well as the formation of reliable interconnects. The complexity of assembling multi-chiplet packages requires new factory automation solutions that can maximize product quality and factory utilization.

High resolution patterning can be achieved with materials and technologies from traditional front end processing, including PVD, Dry Etch, CVD and ALD. With its broad portfolio of semiconductor and display fabrication technologies and products, Applied Materials is addressing the challenge of delivering Front End manufacturing capability at Back End cost requirements. This presentation will highlight Applied innovations that enable panel level packaging and the factory of the future.

Len Tedeschi photo

Len Tedeschi

VP & GM Core Packaging Products

Applied Materials