10:10 – 10:35

Keynote (Yield): Optimizing Yield at Scale Using Digital Twins 

As AI compute demand accelerates, semiconductor manufacturing faces unprecedented pressure to deliver high-yield, cost-effective chips at scale. Traditional manual yield tuning struggles to manage the complexity of advanced nodes such as Intel’s 18A. This talk explores how Intel leverages a comprehensive AI/ML-driven approach encompassing Design-Technology Co-Optimization (DTCO), advanced process control, and yield & process analysis to transform yield optimization.

By integrating digital twins of facilities, equipment, process, and logistics with real-time factory automation data, Intel simulates complex fab operations to proactively detect and prevent yield-impacting issues. Advanced AI techniques identify critical correlations across hierarchical data levels from wafer to die enabling rapid root cause analysis and accelerating yield feedback loops. Turning vast amounts of data into actionable insights requires not only sophisticated algorithms but also deep manufacturing expertise and disciplined execution. Leveraging decades of manufacturing excellence and breakthrough innovations like 18A PowerVia technology, Intel has developed a scalable framework that drives faster innovation , cost control, and robust yield performance to meet the surging demand of AI compute.

Attendees will gain a clear understanding of the complexities inherent in advanced process nodes and how evolving data-driven methods such as AI/ML and digital twin-based simulations are essential to managing these challenges. These approaches are becoming increasingly critical in today’s AI-driven semiconductor manufacturing landscape.

Prashanth Aprameyan

GM Silicon Business Line (Advanced Technologies)

Intel Foundry