High density interconnects is the key for achieving high bandwidth package which is required mainly for HPC and other high-end applications. Heterogeneous integration is one of the robust and cost effective solution to support the increasing demands in compute performance and memory areas. Chip level heterogeneous integration or Chiplet technology is an encouraging low cost solution for advanced Si node expensive die. These die can be from a range of wafer sizes fabricated in different technology nodes from various semiconductor sources. Chiplets are small IC dies with specialized functionality, designed to combine to make up a bigger and complex chips required for high performance applications. This advanced packaging type creates many challenges in assembly and manufacturing yield.

There are various ways of making Chiplet package depending on the end application requirement, cost and ease of supply chain. Fine line and space standard substrate, Si interposer, RDL interposer, embedded bridge die in RDL interposer, etc. are some of the popular options currently available in the market for Chiplet packaging. This paper will explore the various processes and technologies to achieve a cost effective and high performance Chiplet package.