27-28 August 2025
Suwon
11:30 – 11:50
Is Heterogeneous Integration (HI) ready for Artificial Intelligence (AI)?
Moore’s law has helped us for 5+ decades through monolithic integration with doubling of transistors every two years. With the introduction of deep learning in 2012, compute demand has been out pacing Moore’s law. Progress in AI over the last decade has been hardware driven with large scale models exploiting the large transistor connectivity available. More recently there appears to be a shift towards developing software efficiencies, along with hardware advances. Nevertheless, the need for more and more transistors will never cease, and hence continuation of Moore’s law becomes a necessity. Heterogenous Integration (HI) is taking the front seat to continue Moore’s law.
But is HI ready to take on this challenge for the next decade? Are we geared towards saving our planet from an energy crisis? What are some of the key technologies that we need to focus on for HI? This presentation will address some of these questions by focusing on challenges as well as recent progress.
Madhavan Swaminathan, Ph.D.
Penn State University
Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center chimes.psu.edu. Prior to joining Penn State, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC) – a graduated NSF-Engineering Research Center (ERC), Georgia Tech (GT). Prior to GT, he was with IBM working on packaging for supercomputers. Prof. Swaminathan’s interdisciplinary research on semiconductor packaging and systems integration over the years have resulted in 650+ technical publications, 200+ invited presentations (seminars, keynotes, panels), 3 books, 5 book chapters, 31 patents, 33 best paper and student paper awards, 5 GT awards, 2 start-ups, and several international recognitions with the recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (technical field award) for “contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems”. He is also the founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He received his MS and PhD degrees in Electrical Engineering from Syracuse University, USA.
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