Salah Nasri leads the International Semiconductor Industry Group, founded in 2010, it is a global leading semiconductor association known for its flagship platforms (The International Semiconductor Executive Summits), uniting top executives, government officials, researchers, and investors from around the globe to address challenges and opportunities in chip manufacturing and technology innovation. He guides the association in shaping crucial industry dialogues—ranging from trade regulations to cutting-edge chip design—and fosters collaborations that drive the future of the semiconductor sector. Salah studied International Relations and Economics at Oxford University, Loughborough University and in 2024 graduated from the Stanford Graduate School of Business Executive Program.

Simi Sherman is Co-Founder and CEO of Chips & Wafers, a semiconductor data and research platform, and VP of Research with ISIG.

After six years at a Buy-Side global equities Hedge Fund, where he was a Partner and led semiconductor research, Simi Co-founded Chips & Wafers. Working together with ISIG, Chips & Wafers provides semiconductor companies and investors with timely and actionable data they utilize in making more informed decisions.

Yu-Po Wang received Ph.D. in Mechanical Engineering from Binghamton University, State University of New York , U.S.A.

In 1997, he started career at Gintic Institute of Manufacturing Technology in Singapore.

He joins SPIL in 1998 and leads the R&D Package Application and Technology Support Team in substrate/package design, material characterization and advanced package.

Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has over 83 patents in US.

IEEE Electronics Packaging Society Board of Governors (BoG) member from 2025

IEEE Electronics Packaging Society Taipei Chapter Executive Committee from 2025

C.S. is a 30+ years’ veteran of semiconductor industry.

Ever since joined TSMC, he has been working in various technology R&D fields and Operations.

He took various managerial positions in RD Process Module, SRAM, DRAM and Embedded DRAM.

CS also led TSMC Mask RD and Operation Division before taking the position of VP in Specialty Technology RD.

CS received his PhD in Chemical Engineering from WPI (Worcester Polytechnic Institute)

Joris Van Campenhout is Fellow Silicon Photonics at imec and senior director of imec’s industry-affiliation R&D program on Optical I/O, which targets the development of scalable short-reach optical interconnect technology based on silicon photonics. Prior to joining imec in 2010, he was with IBM’s TJ Watson Research Center (USA), where he developed silicon electro-optic switches. He obtained a PhD degree in Electrical Engineering from Ghent University (Belgium) in 2007, for his work on heterogeneous integration of InP lasers on silicon. Joris has been granted 15+ patents and has authored or co-authored over 100 papers in the field of silicon integrated photonics, which have received 15000+ citations.

Kathy Yan, currently Director of New Technology & System Integration, Advance Packaging and Test at TSMC. She is now in charge of new CoWoS-R organic interposer technology RD development for high speed HPC application, advanced packaging mechanical and thermal simulation & validation. She has been also managing new product co-development projects for system customers, across multiple packaging architecture including InFO POP, InFO-SOW, CoWoS-S and CoWoS-R. In addition She is the key player in TSMC 3D Fabric Alliance as the Memory Eco-system program owner. Prior to joining TSMC, she spend most of her career at Intel Advanced packaging RD and Medtronic technology Center in Arizona, US. She has a PhD in Electrical Engineering and Master in Material Science from Auburn University.

Boon-Pin Ong (Boon) leads the Advanced Packaging Technology Development (APTD) in Micron Taiwan, focusing on enablement of advanced packaging technology roadmaps for memory and storage solutions.

Prior to his current role, Boon headed Micron’s DRAM Technology Development in Taiwan responsible for delivery of the industry’s first samples of 1γ (1-gamma), sixth-generation (10nm-class) DRAM node-based DDR5 memory.

Boon has been with the company for 20 years and served in Micron’s global semiconductor manufacturing and technology development sites in Singapore, the United States, Japan, and Taiwan.

Dr. Raja Swaminathan is the Corporate Vice President of Packaging at AMD, spearheading the development of AMD’s advanced packaging and heterogeneous integration roadmap. With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan’s expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple’s Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators. Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to their name, Dr. Swaminathan was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology.

Dr. Lo received his Ph.D. from National Taiwan University and joined Industrial Technology Research Institute to work in advanced electronic packaging, such as WLP, 3D IC/3D stacking, fan-out, heterogeneous integration technology for more than 20 years, 85 papers and 40 patent granted. Currently, he also serves as TWG chair of IoT Chapter of IEEE Heterogenous Integration Roadmap(HIR) and chairman of International Microelectronics Assembly and Packaging Society (IMAPS)-Taiwan chapter.

Education:

• Ph.D. Chemistry, 2001, National Taiwan University

Experience:

• 2012~2021, Vice President, Unimicron Technology Corp.
• Advanced substrate, panel level RDL and glass substrate Technology
• 2001~2012, Deputy R&D Director. ITRI/EOSL
• 3DIC, wafer level stacked & 8” and 12” CIS TSV package technology
• Chip embedded in rigid and flexible substrate technology
• Flexible LED lighting package technology

Dr Hamid Azimi, formerly Corporate VP, Director of Substrate Packaging TD of Intel. He was responsible for advanced substrate packaging for all Intel logic products across substrate suppliers’ factories, as well as the company’s two internal substrate R&D factories. These R&D factories are the birthplace of panel level die embedding technology and play a crucial role for enabling EMIB, the key technology to Intel’s data-centric business and heterogenous packaging. His team works with equipment, material, chemical and substrate suppliers to develop Si-fab backend-like technologies for panel level advanced packaging, and transfer technologies to Intel supplier factories to meet the demand of future Intel products.

Kam currently serves as Senior Director at TSMC Advanced Packaging Technology and Service, which he joined in 2022. He specifically manages the TSMC Testing RD, Testing operations and backend turnkey operations. He has extensive experience in semiconductor industry, having worked 27 years at Intel, in various roles in technology development, product development and high volume manufacturing. He previously held the role of Vice President of Intel product development and engineering.

Formal education:
Physics studies @ University of Muenster, Germany – Institute of Materials Physics
PhD in Materials Physics @ University of Muenster, Germany – Institute of Materials Physics

Professional career:
2015 – 2016 Post Doc @ University of Muenster – Institute of Materials Physics
2017 – 2021 Materials Scientist Innovation @ Heraeus Precious Metals – Functional Materials
2021 – 2022 Team Lead Innovation @ Heraeus Precious Metals – Functional Materials
2022 – 2024 Head of Innovation @ Heraeus Precious Metals – Functional Materials
2024 – today Global Head of Innovation @ Heraeus Precious Metals – Functional Materials
2018 – today IP-Manager @ Heraeus Precious Metals – Functional Materials

Senior Product Line Manager for Acoustic Technologies at Nordson Test & Inspection for the Optical Sensor & Metrology division (OSM). Overseeing the development and implementation of advanced acoustic inspection systems tailored for the semiconductor market.

Introduction of SpinSAM™ Acoustic Micro Imaging system for wafer applications. This innovative solution utilizes a unique spin scan method enabling very high throughput for acoustic inspection. Its modular design allows for simultaneous scanning of up to four wafers for continuous operation while ensuring minimal downtime during maintenance.

Integration of Artificial Intelligence (AI) and Machine Learning (ML) in the acoustic inspection processes. Leveraging AI/ML to revolutionize image analysis within acoustic inspection aiming to significantly reduce the time required for complex sample analysis.

Eric Lee is the CEO of Scientech Corp. and Chairman of Yayatech. He joined Scientech in 2004, following nearly a decade at UMC, where he held positions in both Taiwan and Singapore from 1995 to 2004.

In addition to his leadership roles at Scientech and Yayatech, Eric serves as President of the International Semiconductor Executive Summit (ISES) Taiwan. He is also a part-time professor in the Advanced Packaging Master’s Program at National Taiwan University of Science and Technology.

Eric contributes actively to the industry through his roles as a member of the SEMI Taiwan Advanced Packaging Committee and as a director of the Taiwan Electronic Equipment Industry Association.

LIM Choon Khoon (CK) is a Senior Vice President and Chief Executive Officer of Semiconductor Solutions Advanced Packaging (AP).

CK’s career spans key engineering, manufacturing, and regional functional and global general management roles with several global semiconductor companies. As Chief Executive Officer of the Segment’s AP Business Group, he helps provide the industry’s leading first-level interconnect technologies covering leading AP First Level Interconnect (FLI) technologies for logic, HBM, Si Photonics & Co-Packaged Optics, wafer die singulation solution for advanced fabricated wafers and Panel ECD for fine Line/Space organic and glass substrate & Wafer PVD, that are well-positioned to serve and to scale with the most demanding AP needs.

CK holds a Bachelor of Science (Honours) in Production Engineering and Production Management degree from the University of Nottingham, United Kingdom

Yong Hoon (Joshua) Yoo has been involved in the static control industry since 1994 for ionization, ESD measurement and high voltage power business operation in semiconductor, flat panel displays and automotive industry. He has been a member of EOS/ESD Association since 2000 and served as an Elected Board of Director in 2016 – 2018. He is the founder and president of Korea EOS/ESD Association since 2011. He is a member of Institute of Electronics and Information Engineers (Korean IEEE) since 2021. He is serving industry as Korea President of International Semiconductor Executive Summits (ISES) since 2024.

He started his volunteering activities on EOS/ESD Association since 2013 as an active working group members and technical program committee members of annual symposium for multiple events of ESD Association. With his leadership, Korea EOS/ESD Association very strongly presents and annual events over 10 years. He is pioneer for flat panel display (FPD) static issue analysis and resolved problems. In recently, he found a root cause of ESD yield losses in AI chip manufacturing environment and improved yield over double digits.

He is an iNARTE certified ESD Engineer in 2007 and the EOS/ESD Association certified Professional ESD Program Manager in 2011. He has 14 patents for ionization system and ESD testing technologies.

Vikram Turkani, serves as the Director of Technology Partnerships and Strategic Business Development at PulseForge Inc., a prominent technology company specializing in advanced packaging solutions based in Austin, Texas. In this pivotal role, Vikram is instrumental in steering the development and implementation of cutting-edge technologies at PulseForge. Through close collaboration with global technology partners, he ensures the successful transition of these state-of-the-art solutions into practical applications within the market.

Beyond driving the development of innovative technologies, Vikram actively engages with PulseForge’s customers, facilitating the seamless adoption of these innovations on a large scale. In addition to his professional pursuits, Vikram enjoys hiking Texas hill country and exploring the vibrant Austin food scene.

Experience

• GM Taiwan, Camtek, 2013 – Present
• Director Taiwan, ASML, 2011 – 2013
• Director Taiwan, Air Liquide, 2009 – 2011
• Sr. AM SEA, Nanometrics Inc., 1998 – 2009
• Director & Associate Professor, Yuanpei Scientific University, 1996 – 1998

Education

National Tsing Hua University
Ph.D., Physics, Nuclear Science 1988 – 1991

As taking on the role of General Manager of Camtek Ltd.’s Taiwan branch since 2013, leading to gain a clear understanding of the company’s existing business model and the challenges it faced, laying the foundation for a comprehensive growth strategy.

The growth strategy began delivering measurable results in 2015, when the company achieved its highest global annual sales in its sector. Since then, it has maintained an impressive 30% year-over-year growth and received numerous industry accolades.

This management philosophy has led to remarkable outcomes. The Taiwan branch has consistently achieved strong annual performance, rapidly expanded its market share, and emerged as a market leader in Taiwan’s advanced semiconductor back-end packaging, testing, inspection, and metrology sector.