Powertech Technology Inc.
Company Profile
Powertech Technology Inc. (PTI), the world’s leading OSAT, was founded in 1997. We serve the international customers with services including chip bumping, chip probing, IC assembly, final testing, burn in, and system level assembly. In 2017 PTI expanded the production base to Japan to serve the local automotive electronics and IoT market. And in 2018, PTI began the construction of the newest Fan Out Panel Level Package manufacturing facility in Hsinchu Science Park.
PTI has over 18,000 employees world wide, and manufacturing facility located in Taiwan, China and Japan. PTI dedicates her efforts in developing advanced technologies, while carrying on as the world’s leading memory packaging and testing solution provider. Through strategic alliances and resource integration, PTI group relentlessly marches onward in the semiconductor packaging and testing field.
We drive our future growth with outstanding quality, cost, and delivery. Promise, Technology, and Integration represents our core values. With our ideaology, strategy, and core values, PTI stands as the world class OSAT.
Product & Services
PTI offers the services inculding Final test, Chip Probe, IC Packaging, Module Assembly, Quality Management. And provide wide range of technology solution for IC packaing including Panel Level Fan Out, TSV solution, Bumping, Flip chip, Antenna in Package.
-Panel Level Fan Out
Fan-out packaging is going to become the mainstream for high-end device application, especially for multi-die, heterogeneous integration for both active & passive devices. High density interconnect, excellent performance in electrical performance and power consumption can also be achieved by panel FO. PTI’ Panel level FO packaging offers the merits of high production efficiency with better utilization & unit output in comparison to wafer level FO.
Solution: CHIEFS® / CLIP® / PiFO® / BF2O®
TSV Solution-3DIC
3D IC is one kind of heterogeneous technology which is integrated vertically by Si wafers or chips. The interconnection is composed by u-bumps and Through Silicon Via (TSV). TSV fabrication is regarded as the heart of 3D IC because it provides the advantages of shortening the interconnection path, high function density, low power consumption, smaller form factor and high performance; these benefits make 3D IC get commercial success in some specific applications, such like HPC and AI.
TSV Solution-CMOS Image Sensor
CMOS Image Sensor (CIS) is an electronic device that converts an optical image into an analog signal. Recently, the most attractive is stack-CIS, that BSI CIS, memory wafer and Image Signal Processor(ISP) wafer are vertically integrated and higher performance, lower power consumption would be the advantages for high-end application.
Bumping
Wafer bumping is a metal bump that grows on a wafer, and each bump is an IC signal contact. Unlike conventional interconnection through wire-bond, bond pads are placed at peripheral area , IO pads for bumping could be distributed all over the surface of the chip, thus chip size could be shrunk and electrical path could be optimized.