Salah Nasri leads the International Semiconductor Industry Group, founded in 2010, it is a global leading semiconductor association known for its flagship platforms (The International Semiconductor Executive Summits), uniting top executives, government officials, researchers, and investors from around the globe to address challenges and opportunities in chip manufacturing and technology innovation. He guides the association in shaping crucial industry dialogues—ranging from trade regulations to cutting-edge chip design—and fosters collaborations that drive the future of the semiconductor sector. Salah studied International Relations and Economics at Oxford University, Loughborough University and in 2024 graduated from the Stanford Graduate School of Business Executive Program.

Mr. Tomoshige NAMBU has served as the Director for IT Industry Division at the Ministry of Economy, Trade, and Industry (METI) in Japan since July 2025. He leads METI’s AI and semiconductor strategy.

Prior to his current position, he spent 3.5 years in NYC and Washington D.C. from December 2021 to June 2025, serving as Special Advisor for METI at the New York Office of the Japan External Trade Organization (JETRO). He was a senior METI representative in the US, covering trade and economic security policies.

During a more than 20-year career at METI, Mr. Nambu has held responsibilities across a diverse range of public policy areas. He was involved in the formulation of Japan’s economic policy in 2018-2021 as the Director for Macroeconomic Policy at METI. He also assumed the duty of Cabinet Counselor, drafting policy proposals on economic growth strategy under the direction of the Prime Minister’s office.

He was stationed in Washington D.C. as the Trade Attaché at the Embassy of Japan in the U.S. from 2012 to 2015 and worked on several bilateral trade issues such as TPP and energy exports from the U.S.

He joined METI in 2002 after receiving a Bachelor of Law from the University of Tokyo. He also holds an L.L.M from Harvard Law School. He served as the Asia Program Fellow at the Rajawali Foundation Institute for Asia in Harvard Kennedy School in 2009-2010. He currently lives in Tokyo with his wife.

Joined IBM Japan in 1987, and later moved into IBM Research, after acquiring his master degree in EE&CS from MIT in 1995. In 2006, transferred to IBM Watson Research Center. He had served as a Director of IBM Research-Tokyo, CTO of IBM Asia Pacific Region, and VP of R&D in Japan, before becoming CTO of IBM Japan. He became Vice President of IBM Japan in 2023 and joined a member of BoD of IBM Japan in 2024.He is appointed as a member of Semiconductor and Digital Strategy Advisory Panel under the Ministry of Economy, Trade and Industry (METI).

Deepak Kulkarni is a Fellow, Advanced Packaging at AMD. Deepak has over 15 years of experience in packaging technology development. Over the years, he has held several leadership positions driving substrate technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds 17 patents and nineteen publications on various aspects of packaging such as 2.5D/3D architectures, DFM/DFY and AI techniques applied to yield management. His contributions to the semiconductor industry have been recognized by an Intel Achievement Award, Next 5% award (AMD) and best paper award (ITHERM). Deepak holds a PhD from the University of Illinois Urbana-Champaign with a major in mechanical engineering and a minor in computational science.

Joined Toshiba, Semiconductor Device Engineering Labs. in 1988 and engaged in development of advanced SRAM/Logic technologies. 2006-2010: engaged in development of 32nm~20nm CMOS platform technologies with IBM as Toshiba’s representative (VP of R&D). 2013 Senior Manager of Advanced Memory Technology Development Dept. 2022 Director of Memory Technology R&D Center. Joined Rapidus Corporation in April 2023.

Lode Lauwers is Senior Vice President Business Development and Strategy in IMEC, the nanoelectronics R&D Center in Leuven, Belgium. His current focus is to architect new global R&D collaborations and related business models, in line with semiconductor technology initiatives in various continents currently in conception. In that role he also guides imec’s Corporate Business Development strategies in nanoelectronics. Since he joined IMEC in 2005, he had various leading roles in IMEC’s technology business development and partner relation management. He has been driving over 2 decades the build-out, growth and business foundations of imec’s flagship core program with leading IC manufacturers, foundries, equipment and material suppliers and design and system houses. Earlier, he has been general manager of an ASIC design house, part of a US-based ASSP provider for the telecom industry, and scientific advisor for government funding in local and European cooperative networks in micro-electronics and telecommunications. He has a PhD in Electrical Engineering from KU Leuven.

Takahiro Ogura is a seasoned leader in high-performance computing with over 20 years of experience. He currently heads the AI Computing Division at Preferred Networks (PFN), overseeing the company’s critical computing infrastructure technologies including the MN-Core™ series of AI semiconductors and in-house supercomputers. Prior to joining PFN, he served as the after-sales service manager for domestic high-performance computing clients at Fujitsu, where he began his career as a systems engineer working on supercomputer systems projects. A notable career highlight was his instrumental role in the design and development of the Fugaku (Post-K) supercomputer at Japan’s national research and development agency RIKEN. Ogura received a Master’s degree from Tsukuba University’s Systems and Engineering program in 2005.

Hidenori Abe is CTO for semiconductor materials and Executive Director of Electronics Business Headquarters at Resonac. He leads R&D and strategy for electronic materials in semiconductors, substrates, and displays. Previously, Mr. Abe served as the head of the Electronics R&D Center and Packaging Solution Center, where he contributed to advanced packaging development through open innovation. Notably, in 2021, he directed the launch of JOINT2, a consortium targeting 2.xD and 3D packaging technologies. He received a master’s degree in chemical engineering from Tokyo Institute of Technology, Japan, and a master’s degree in the Executive MBA program from the University of Oxford, UK.

Graduated From Nagasaki University Master’s Degree

(Appointed Dates)
April 1993 　       Joined Toppan Printing Co.,Ltd., Electronics Division
April 1996 　       TOPPAN Kumamoto Technical Research Institute.
April 2002 　       TOPPAN (Corporate) Technical Research Institute
April 2010 　       General Manager, FC-BGA Engineering Department, Toyama Plant
April 2014 　       General Manager, FC-BGA Engineering Department, Niigata Plant
April 2018 　       Head of Technical Development Headquarters Ⅱ, Electronics Division
April 2022 　      Head of Semiconductor Business, Electronics Division
April 2023 　      Executive Officer, Head of Semiconductor Business, Electronics Division
October 2023      TOPPAN Inc. Executive Officer, Head of Semiconductor Business, Electronics Division
April 2025　      TOPPAN Inc. Executive Officer, Head of Semiconductor Subdivision, Electronics Division