未来を牽引する:半導体産業における先進的なパッケージング、AIの統合、そして自動車のイノベーション

08:00 – 08:35

受付(登録)

次世代半導体およびパッケージングソリューションにおけるガラスおよび パネル基板の進化した基板技術

08:40 – 09:00

基調講演

Advanced Packaging Technologies for the AI era

Advanced packaging is enabling unprecedented levels of integration, enabling dense interconnection of logic, memory and optical chiplets, to create a system in a package. In AI & data centric applications, the amount of silicon content in a single package is increasing dramatically every generation. To meet future scaling, high speed signaling and power delivery needs, the package substrate must also evolve significantly. In this talk, we will cover some of the recent advances in the EMIB package platform including multiple scaling vectors such as die to die interconnection pitch, package form factor and the introduction of a bridge with TSV to enable denser and more efficient integration on package. Further, we will also cover the Intel’s latest breakthrough’s in glass core substrates which have superior mechanical, physical and optical properties and can drive dramatic improvements in chiplet integration on a substrate.

ラーフル・マネパリ博士

Intel Fellow & Vice President : Advanced Packaging Technology Development

Intel - Rahul Manepalli Ph.D., Intel Fellow, VP, Director of Substrate Packaging Technology Development

09:00 – 09:20

基調講演

荒木 康 氏

上席執行役員

新光電気工業株式会社 

09:20 – 09:40

Revisiting the Necessity and Challenges of Glass Substrates in 3DIC Advanced Packaging

In 3DIC and HPC packaging, achieving both high-precision assembly and reliability demands a careful balance of material properties. Glass offers low CTE, high flatness, and low dielectric loss, yet faces trade-offs such as TGV reliability and stress management. This study argues that, without clearly defining the necessity of glass, application development lacks momentum. By analyzing these inherent contradictions, we discuss how to interpret and manage the trade-offs between material properties and system reliability, providing insights toward the future direction of glass utilization in advanced packaging.

市川 公也 氏

テクニカル ディレクター

3DIC Research Lab LLC

09:45 – 10:45

ネットワーキング・ビジネスミーティング5・6

10:50 – 11:00

Tailoring through glass via (TGV) dimensions for glass-core panel substrates

Glass-core substrates are redefining advanced packaging by overcoming warpage and thermal management limits of organic materials. Central to this technology are through-glass vias (TGVs), whose precision and density define performance. We present an innovative alkaline etching technology combined with laser modification, enabling unprecedented control of via geometry with taper angles below 1°. Compared to conventional acidic etching, our process delivers higher selectivity, at advanced throughput, and compatibility with industrial considered glass types. This breakthrough enables the scalable production of ultra-high-density TGV substrates—paving the way for next-generation packaging demands.

Holger H. Kuehnlein氏, PhD,

SVP Technology

RENA Technologies

11:00 – 11:10

Advanced Packaging Solutions with Direct Atomic Layer Processing (DALP®) Technology

Advanced packaging requires new approaches to achieve heterogeneous integration, energy efficiency, and performance scaling beyond conventional methods. ATLANT 3D’s proprietary Direct Atomic Layer Processing (DALP®) technology delivers a breakthrough by enabling localized, maskless material processing with atomic precision. This unique capability provides unmatched flexibility for next-generation packaging architectures, including 2.5D and 3D integration. By combining speed, cost efficiency, and material versatility, DALP® paves the way for transformative advances in semiconductor manufacturing and packaging innovation.

Maksym Plakhotnyuk 氏, Ph.D.,

CEO & Founder

ATLANT 3D

11:10 – 11:20

Axiom Space 

11:25 – 12:10

Panel Discussion: How Far Can Package and Substrate Scaling Go Beyond 2028?

 

 

モデレーター

市川 公也 氏

テクニカル ディレクター

3DIC Research Lab LLC

Panelist

Deepak Kulkarni, Ph.D.

シニア・フェロー アドバンスド・パッケージング

AMD

Panelist

ラーフル・マネパリ博士

Intel Fellow & Vice President : Advanced Packaging Technology Development

Intel - Rahul Manepalli Ph.D., Intel Fellow, VP, Director of Substrate Packaging Technology Development

Panelist

Monita Pau氏, Ph.D.

Strategic Marketing Director, Advanced Packaging

Onto Innovation

Panelist

阿部 秀則 氏
執行役員 半導体材料研究開発統括

株式会社レゾナック

Panelist

荒木 康 氏

上席執行役員

新光電気工業株式会社 

12:15 – 13:30

昼食

最先端のイノベーションでパワー半導体と自動車の未来を形作る

13:35 – 13:55

基調講演

次世代車両が直面する電力課題と村田製作所の技術革新への取り組み

Vehicle architecture is undergoing rapid transformation driven by autonomous driving, IoT integration, AI implementation, and the shift toward Software-Defined Vehicles (SDVs). The overall power consumption of vehicles is increasing due to the rise in electronic control units and the adoption of high-performance processors. While low-power design, wide bandgap semiconductors, and thermal management technologies are being developed, efforts are also underway to develop in-motion charging and transition to 48V architectures.

Requirements for electronic devices in new architectures and Murata’s initiatives will be reported.

岩坪 浩 氏

代表取締役副社長

株式会社村田製作所

13:55 – 14:15

半導体製造工場におけるAMHSの現在と未来を探る

Automated transportation in semiconductor fabs began with front-end processes in 1980s. It has grown in scale and expanded to advanced back-end operations. Recently we are also receiving requests to handle materials and tools. Beyond wafer transportation, by “Full Fab Automation”, where we fully automate the movement of goods throughout the entire factory, we aim to contribute to the ever-growing semiconductor industry.

村田大介 氏

代表取締役社長

村田機械株式会社

14:15 – 14:35

モビリティと持続可能性の推進:次世代パワーデバイスと統合パワー エレクトロニクスに向けたデンソーのビジョン

Achieving zero accidents and zero emissions demands breakthrough innovation in automotive power electronics. DENSO, drawing on its Tier1 expertise and the advanced semiconductor R&D of MIRISE Technologies, is driving progress in wide bandgap semiconductors, advanced packaging solutions, and next-generation control technologies through integrated system development. This approach enables higher efficiency and reliability in electrified vehicles and accelerates the transition to sustainable mobility. Through global collaboration and next-generation solutions, DENSO is committed to shaping a future where mobility harmonizes with environmental stewardship and societal wellbeing.

松ケ谷 和沖 氏

情報開発センター シニアディレクター

株式会社デンソー-

14:35 – 14:45

スマート材料、より賢いシステム:設計基板による3D集積の実現

The semiconductor industry is entering a decisive phase where traditional 2D scaling is no longer sufficient to sustain performance, energy efficiency, and cost targets. The path forward lies in 3D integration, where materials innovation and substrate engineering play a pivotal role. At Soitec, our mission is to provide the foundational technologies that make this transition possible.

Engineered substrates represent a strategic enabler for the next era of computing. By tailoring the substrate to the device, we unlock unique advantages: superior electrical isolation, reduced power consumption, enhanced thermal performance, and the ability to integrate diverse materials seamlessly. This flexibility is essential to meet the diverse requirements of high-performance computing, mobile communications, automotive intelligence, and edge AI.

At the heart of this innovation is Soitec’s Smart Cut™ layer transfer technology. This breakthrough makes it possible to detach and transfer ultra-thin crystalline layers with atomic precision, enabling stacking and heterogeneous integration at a scale and quality unmatched in the industry. With Smart Cut™, we can bring logic, memory, and interconnect layers closer together, shortening critical paths, reducing latency, and dramatically increasing bandwidth density.

What this means for the industry is profound: engineered substrates and precision layer transfer redefine the scaling roadmap. They extend Moore’s Law where transistor scaling alone cannot, and accelerate “More-than-Moore” solutions by enabling chiplet architectures, advanced system-in-package, and vertically integrated designs.

As we look ahead, Soitec is committed to driving collaboration across the ecosystem—foundries, device makers, and system integrators—to unlock the full potential of 3D integration. By aligning materials innovation with system-level needs, we ensure that the semiconductor industry continues to deliver the performance and efficiency breakthroughs that power our digital society.

Christophe Maleville氏, Ph.D,

Chief Technology Officer and Senior Executive Vice President of Soitec’s Innovation

Soitec

14:50 – 15:50

ネットワーキングとビジネスミーティング7

15:55 – 16:15

Gaurang Shah 氏

Vice President, Power Product Group

Renesas Electronics

16:15 – 16:25

Powering the Future of EV’s and Data Centers by Driving Power Density

As the world moves towards global electrification, innovation on multiple fronts is required to create highly efficient EV systems. Innovations on control systems, modules for power stages, semiconductors, new materials for thermal management and operating systems at higher frequencies allow for EV systems to become more efficient. In this talk, we will discuss new semiconductors that can switch high voltages at higher frequencies. The advantages of switching at higher frequencies translates to higher efficiency of the EV motor and inverter leading to lower costs for the EV. We will also discuss thermal management options for the power stages so we can push the existing semiconductors to deliver more power increasing the power density of the system.

Dinesh Ramanathan, Ph.D.

Senior Vice President, Corporate Strategy

onsemi

16:25 – 16:55

未来の労働力:日本の長期競争力に向けた半導体人材の育成・訓練・啓発

モデレーター

サラ・ナスリ

CEOおよび共同創設者

International Semiconductor Industry Group (I.S.I.G.)

Panelist

青砥なほみ

教授  (Professor by Special Designation)

広島大学

Panelist

遠藤 哲郎 教授

センター長

東北大学 国際集積エレクトロニクス研究開発センター

Panelist

Hitoshi Wakabayashi

Professor

Tokyo University of Sicence

16:55 – 17:00

閉会の挨拶

須原忠浩

CEO

TSSC

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