Jim Li, Ph.D.
VP, Fan-out, Power Module Development and Engineering System Management
No summit linked
- Jim Li (Chung-Li) joined ASE in 1999 as a Sr. engineer for new package development. He served several roles as a manager for design team, modeling and measurement labs, and director for business promotion and Customer Engineering Integration.
- He is now Vice President for Fan-out, Power Module Development and Engineering System Management.
- Jim Li received Ph.D. from Chemical Engineering, Northwestern University, and holds more than 10 patents related to semiconductor packaging.
Company Profile
ASE is the leading global provider of semiconductor manufacturing services in assembly and test. With a proven track record spanning almost 40 years, ASE today is at the forefront of flexible, powerful, integration technologies that achieve criteria for improved power, performance, area, and cost requirements. Our comprehensive toolbox leveraging innovative technologies, such as die interconnection, wafer level fan out, embedded devices, conformal and compartmental shielding, integrated antenna, and others, are being refined and enhanced to support future generations of system integration. Heterogenous Integration through SiP is enabling significant innovation across dynamic application areas including AI, 5G, automotive, mobile, IoT and more. Our industry is driven by innovation, and through ASE’s miniaturization technologies, we are enabling transformative solutions that are literally changing lives, from health to transportation, from Robotics to AI, from IoT to 5G.
Website: ase.aseglobal.com
Jerry Tzou
Formerly Director of Advanced Packaging Business Development of TSMC
No summit linked
Jerry Tzou recently retired from TSMC, where he wrapped up as Director of Advanced Packaging Business Development. He spearheaded the strategic growth of TSMC’s 3DFabric® platform— CoWoS®, InFO, TSMC-SoIC®, TSMC-SoW™, and COUPE™ for Co-Packaged Optics (CPO) —tying it to TSMC’s advanced silicon innovations. This work fueled next-generation applications in AI-driven high-performance computing, mobile, automotive, and IoT. Through synergistic collaboration with customers and partners inside and out, he drove significant revenue growth in advanced packaging.
Jerry’s 40-year semiconductor career included diverse roles at TSMC, a stint as VP of Product Operations at Global Unichip Corporation (GUC), a TSMC-affiliated design foundry, and advanced packaging work at Apple, National Semiconductor, Cirrus Logic, and select Silicon Valley startups. With a Master’s in Materials Science and Engineering from UC Berkeley, his expertise spans semiconductor packaging, operations, and business development.
Company Profile
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
TSMC deployed 288 distinct process technologies, and manufactured 11,878 products for 522 customers in 2024 by providing the broadest range of advanced, specialty and advanced packaging technology services. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.
Mostafa Aghazadeh
President of Chiplink Consulting LLC / Formerly CVP, Director of Dir Prep & Assembly Technology Development of Intel
No summit linked
Mostafa Aghazadeh is a seasoned industry leader and the President of Chiplink Consulting LLC, where he advises companies on advanced packaging technology and manufacturing.Previously, he spent 40 years at Intel, holding various leadership roles in Assembly & Test Technology Development. As a Corporate Vice President, he led Intel’s assembly process, materials, and equipment technology development.He currently serves on the technical advisory boards of BESI, Brewer Science, and IMEC and previously chaired the INEMI Board of Directors. He was also a member of Arizona State University’s New Economy Initiative and the School of Manufacturing Systems and Networks Industry Advisory Board.
Company Profile
Provide consulting services in the areas of microelectronics advanced packaging technology, manufacturing, and supply chain including process, equipment, and materials.
Consulting Services
Jim Lin, Ph.D.
VP of Advanced Technology & Wafer Level Package Operation
No summit linked
Dr. Jim Lin is Vice President of Advanced Technology & Wafer Level Package Operation. He is in charged of advanced packaging R&D, Business and Operation in PTI. Prior to BU head, Dr. Lin was AVP of Memory Packaging Research & Development. Dr. Lin joined PTI in 2006, led the development of memory packaging technology. Developed technologies including 8 to 32 chips memory stacking package, system integrated package of SSD, Package on Package(PoP), Heterogeneous multi-chip package(MCP), 3D TSV interconnection High Bandwidth Memory(HBM) and Fan-out Panel Level Package (FOPLP). Dr. Lin received his M.S. and Ph.D. degree both from National Tsing Hua University in Power Mechanical Engineering.
Company Profile
Powertech Technology Inc. (PTI), the world’s leading OSAT, was founded in 1997. We serve the international customers with services including chip bumping, chip probing, IC assembly, final testing, burn in, and system level assembly. In 2017 PTI expanded the production base to Japan to serve the local automotive electronics and IoT market. And in 2018, PTI began the construction of the newest Fan Out Panel Level Package manufacturing facility in Hsinchu Science Park.
PTI has over 18,000 employees world wide, and manufacturing facility located in Taiwan, China and Japan. PTI dedicates her efforts in developing advanced technologies, while carrying on as the world’s leading memory packaging and testing solution provider. Through strategic alliances and resource integration, PTI group relentlessly marches onward in the semiconductor packaging and testing field.
We drive our future growth with outstanding quality, cost, and delivery. Promise, Technology, and Integration represents our core values. With our ideaology, strategy, and core values, PTI stands as the world class OSAT.
PTI offers the services inculding Final test, Chip Probe, IC Packaging, Module Assembly, Quality Management. And provide wide range of technology solution for IC packaing including Panel Level Fan Out, TSV solution, Bumping, Flip chip, Antenna in Package.
-Panel Level Fan Out
Fan-out packaging is going to become the mainstream for high-end device application, especially for multi-die, heterogeneous integration for both active & passive devices. High density interconnect, excellent performance in electrical performance and power consumption can also be achieved by panel FO. PTI’ Panel level FO packaging offers the merits of high production efficiency with better utilization & unit output in comparison to wafer level FO.
Solution: CHIEFS® / CLIP® / PiFO® / BF2O®
TSV Solution-3DIC
3D IC is one kind of heterogeneous technology which is integrated vertically by Si wafers or chips. The interconnection is composed by u-bumps and Through Silicon Via (TSV). TSV fabrication is regarded as the heart of 3D IC because it provides the advantages of shortening the interconnection path, high function density, low power consumption, smaller form factor and high performance; these benefits make 3D IC get commercial success in some specific applications, such like HPC and AI.
TSV Solution-CMOS Image Sensor
CMOS Image Sensor (CIS) is an electronic device that converts an optical image into an analog signal. Recently, the most attractive is stack-CIS, that BSI CIS, memory wafer and Image Signal Processor(ISP) wafer are vertically integrated and higher performance, lower power consumption would be the advantages for high-end application.
Bumping
Wafer bumping is a metal bump that grows on a wafer, and each bump is an IC signal contact. Unlike conventional interconnection through wire-bond, bond pads are placed at peripheral area , IO pads for bumping could be distributed all over the surface of the chip, thus chip size could be shrunk and electrical path could be optimized.
Marvin Liao, Ph.D.
Advisory Board Member
No summit linked
Education :
- Ph.D., Materials Science, University of Texas, USA, 1989
- Bachelor, Materials Science, Tsing Hua University, Taiwan, 1979
Experience :
- TSMC, Advanced Packaging Technology and Service, 2011 ~ 2022
- TSMC, Special Project, 2009 ~ 2010
- TSMC, Fab 6 Director, 2003 ~ 2009
- Chartered Semiconductor, 1997 ~ 2002 (Singapore)
- Applied Materials, 1994 ~ 1997 (USA)
- SGS Thomson Microelectronics, 1990 ~1994 (USA)
Company Profile
Established in 2010, the International Semiconductor Industry Group (ISIG) is a prestigious and trusted global platform, known for fostering collaboration and driving innovation across the semiconductor industry. With a strong foundation through its International Semiconductor Executive Summits (I.S.E.S.), ISIG orchestrates influential regional summits across the U.S., Middle East, Europe and Asia, fully endorsed by local governments and leading companies throughout the semiconductor supply chain.
At ISIG, we are more than just event organizers—we serve as a catalyst for shaping the future of the semiconductor industry. Through high-level executive recruitment, expert consultation, and strategic investor engagement, ISIG empowers global collaboration, helping industry leaders connect, collaborate, and innovate. Our vision is to create a trusted network that transcends borders and disciplines, uniting government officials, academic experts, and investors to tackle the most pressing challenges and seize the greatest opportunities in the semiconductor ecosystem.
Together, we ensure the semiconductor industry remains at the forefront of technological advancement and economic growth, shaping a sustainable future for the global market.
Mike Rosa, Ph.D.
CMO & SVP Strategy
No summit linked
Mike Rosa is chief marketing officer (CMO) and senior vice president responsible for strategy at Onto Innovation. Prior to his current role, Mike served as CMO for Applied Materials ICAPS and Advanced Packaging Groups, where he was responsible for leadership of strategic and technical marketing, marketing communications, charting device segment inflection roadmaps and providing strategic business development support toward M&A activities. He has over 25 years’ experience in semiconductor engineering and technology, with roles that span device design and fabrication, equipment development, marketing and sales. His technical qualifications include B.Eng. (Hons) and Ph.D. degrees in Microelectronic Engineering and an MBA with dual majors in Marketing and Business Strategy. Mike has authored over 40 journal and conference publications and holds over 29 U.S. patents
Company Profile
Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.
General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com
End of content
End of content