Jackie Sturm leads operations for Intel’s multi-billion-dollar Global Supply Chain, which has been cited as a #8 or better for nine consecutive years in Gartner’s Supply Chain Top 25. Her international team supports Construction and Facilities sourcing, Indirect procurement, business continuity, supply chain systems and analytics, and Supply Chain Environmental and Social Governance program, which includes Intel’s first-mover Conflict Minerals initiative. Jackie is a committed advocate for the criticality of value-added manufacturing, engineering and trade as the economic foundations of thriving societies. Within Global Supply Chain, Jackie sponsors targeted advancement programs to address challenges faced by women and unrepresented minorities in technology.

Jackie is a board director for KM Labs and on the board of advisors for Banff International Research Station, Gartner/SCM Word, Howard University Center for Supply Chain Management, and Women’s Business Enterprise National Council (WBENC). Prior to joining supply chain, Jackie held various finance positions at Intel, including CFO for Technology and Manufacturing, as well as at Hewlett Packard, Ridge Computer, and Apple.

Nana Tseng is Chief Procurement Officer of onsemi, a leading semiconductor company rooted in the combined heritage of Motorola and Fairchild. Today, onsemi is driven to innovate intelligent power and sensing solutions focusing in automotive and industrial markets. In her role, she is directly responsible for the procurement and supply partnership strategy, manage multibillion dollar spend ranging from capital equipment, wafer start materials, wafer fab and back end direct and indirect materials, external manufacturing services and corporate services. Prior to joining onsemi, she was the Vice President of Sales at Advanced Semiconductor Engineering (ASE), the world’s largest provider of independent manufacturing services in assembly and test. Her insights on the semiconductor ecosystem and supply chain are built upon her experience working with a broad portfolio of fabless, IDMs, OEMs and EMS companies. Her passion in this industry comes from working with innovative companies committed to bring the next revolutionary technology to the market. Nana was born in Taiwan, grew up in Saudi Arabia, educated in the US, and worked extensively in SE Asia before settling back to Silicon Valley. She has an MBA from MIT Sloan School of Management, and an undergraduate degree from UC Berkeley. In her spare time, she is also very active in her community. She is currently the Vice Chair of Monte Jade West Science and Technology Association, a nonprofit organization focusing to provide mentorship, investment and technology opportunities within the Asian American community and across the Pacific.

Maitreyee Mahajani is Vice President of Fab Operations at Western Digital and manages the Western Digital-Kioxia (previously Sandisk-Toshiba) JV Fabs and is also responsible for managing the NAND supply strategy for Western Digital.

Prior to joining Western Digital, Maitreyee worked at Applied Materials in various technical leadership positions. She has extensive experience developing semiconductor processing equipment which includes the very first 300mm CVD W deposition system, High K/Metal Gate systems and new ALD platforms to name a few.

As Process and Device Integration Engineer at Matrix Semiconductors (Acquired by SanDisk), Maitreyee developed many innovative ideas for building 3D Memory Devices.

Maitreyee holds a Bachelor of Engineering degree from the College of Engineering in Pune, India and a Master’s degree in Material Science from University of Alabama, Tuscaloosa. She holds over 40 patents and is a recipient of YWCA TWIN award (Tribute to Women in Industry). She is on the council for Global Semiconductor Alliance (GSA) Women Leadership Initiative and actively participates in promoting women in engineering at Western Digital and through GSA.

She is based at the company’s San Jose, CA headquarters location.

Ryan Rusnak is a software engineer with a master’s degree in Human Computer Interaction from Carnegie Mellon University. Before co-founding Airspace, Ryan wrote software solutions for the Federal Government. Throughout his career, he has built robots and other projects that have been featured in Popular Science, the Discovery Channel, NBC, BBC, WIRED, Gizmodo, and other media outlets. Ryan teamed up with Nick in 2016 to create Airspace in order to solve the two main inefficiencies in critical logistics: transparency and speed.

Ahmer Syed is a VP of Engineering at Qualcomm in Global Manufacturing Technology and Operations organization. He leads a global team responsible for packaging technology development, NPI, HVM deployment for 5G, mobile, IoT, Connectivity, Automotive, and Compute markets.

A 30+ years veteran of Semiconductor and electronics industry, Ahmer has extensive experience in developing advanced packaging technologies such as Flip Chip, WLCSP, FO-WLP, Package on Package (PoP), QFN, and System in Package (SiP). He has authored and contributed to more than 70 technical papers and articles on advanced packaging and reliability and has been a keynote speaker in various international conferences.

José J. García, Ph.D. is the Managing Director of Wafer Fab Sustainability and Autonomous Enterprise at Analog Devices. He received a B.S. Chemical Engineeering degree from the California Institute of Technology (Caltech) and a Ph.D. Chemical Engineering degree from Cornell University. Upon completion of his Ph.D., José joined Intel’s Portland Technology Development organization to develop Lithographic processes for 6 technologies down to the 32nm node. In 2009, José joined Maxim Integrated to help transform its Beaverton semiconductor facility (fab) to best-in-class safety, quality, output and cost levels thru various process, equipment and procurement directorship positions. Upon Analog Devices’ acquisition of Maxim Integrated in 2021, José secured critical items such as Silicon and Capital Equipment to enable a doubling of output in ADI’s internal fab network with minimal clean room expansion. José is now leading the Manufacturing 4.0 and Net Zero Manufacturing Enablement of ADI’s internal factory network.

Robin Davis is the Director of Business Development at Deca Technologies, an industry leading semiconductor interconnect solutions company. She focuses on identifying new opportunities for the powerful miniaturization and performance benefits of Deca’s M-Series and Adaptive Patterning Technologies. Additionally, she works closely with both internal and customer R&D teams to drive next generation products and technological advances. She is both a contributor and lead inventor on many of Deca’s patents. Previously, Robin fulfilled the role of Senior Solutions Architect at Deca, where she collaborated with customers, suppliers, and Deca’s engineering team to advance package design and interconnect solutions. Robin started her career as a semiconductor packaging engineer at Lattice Semiconductor before transitioning to Advanced Packaging Tools Technical Marketing Engineer at Mentor Graphics (now Siemens EDA). Robin graduated with her BSEE from Portland State University. She is a member of the Tau Beta Pi and IEEE Eta Kappa Nu Honor Societies. Robin also serves as chair of the Diversity, Equity and Inclusivity committee for the International Microelectronics and Packaging Society (IMAPS).

Tony is Sr Director of Global Packaging for Skyworks Solutions. His teams lead advanced packaging R&D and production for wireless semiconductor products, including cellular, infrastructure, automotive, defense, IoT, and others.

He holds degrees in Chemical Engineering from the University of Illinois Champaign-Urbana and an MBA in Technology Management.

Juan is Sr Director of Global Industrial and Systems Engineering for Skyworks Solutions. He has 20 years of U.S. and international experience in semiconductor multi-site manufacturing. His experience ranges from strategic planning to data analytics that drive programs across different functional groups, business units and international sites. Recent initiatives include capacity planning for new technology introduction and the digital transformation of wafer manufacturing sites. He has a MS in Industrial and Operations Engineering from the University of Michigan and a BSEE from the University of California, Irvine.

Prof. Rao Tummala is a Distinguished and Endowed Chair Professor and Director Emeritus at Georgia Tech in USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech in 1993, he was an IBM Fellow and Director of Advanced Packaging Lab(APTL), pioneering such major technologies as the industry’s first plasma display in the 1970’s and the first and next two generations of 100-chip MCM package integration, now called chiplet MCMs, in 1980″s for servers, mainframes, and supercomputers. He is the father of System-on-Package(SOP) concept Vs. System-on-chip (SOC.) As an educator, Prof. Tummala was instrumental in setting up the largest and most comprehensive Academic Center funded by NSF as the 1st and only NSF Engineering Research Center in Electronic Systems Packaging at Georgia Tech. Such a Center, under his leadership, pioneered an integrated approach to research, education, and global industry collaborations. It involved about 30 academic and full-time research faculty,200 Ph.D. and MS students and 50-70 industry and academic collaborators from US, Europe, Japan, Korea, India and Taiwan.. It educated thousands of engineers in packaging in classrooms and labs.,and produced more than 1000 engineers with Ph.D., MS and BS degrees,. He has published about 800 technical papers and invented technologies that resulted in over 110 patents and inventions. He has been pioneering glass-based electronics as the most leading-edge packaging technology beyond Silicon interposers that is targeted to go into production In 2023.

He wrote the first modern handbook in packaging, Microelectronics Packaging Handbook( McGraw-Hill,1988); then 1st undergrad textbook, Fundamentals of Microsystem Packaging(2001); the 1st book introducing the concept of SOP, Introduction to System-on-Package( 2006) and the 2nd edition of Fundamentals of Device and Systems Packaging (2020). He received more than 50 Industry, Academic and Professional Society awards, including. 12Invention and 4 Corporate Awards from IBM, IEEE Award David Sarnoff Award for Industry’s First MCM in 1991 ,ASM-International: Engineering Materials Achievement Award for LTCC in 1992,IEEE CPMT: Sustained Technical Achievement Award in 1992,European Electronic Materials Award from DVM in 1995,,International Microelectronic & Packaging Society’s (IMAPS): Dan Hughes Award in 1997,American Ceramic Society’s John Jeppson Award in 1998,IMAPS’: John A. Wagnon’s Award in 1991,IMAPS: John A. Wagnon’s Award , Named by US News and World Report as one of the 50 Stars in US for US competitiveness in 1999,Total excellence in Manufacturing Award from ASE in 2000,Educator of the Year for Excellence in Teaching, Research, and Innovation in Electronics from the India-America Cultural Association in 2002 andTechno-visionary Award from Semiconductor Industry Association of India in 20110. In addition, he is a distinguished Alumni of

Indian Institute of Science, Bangalore in 2000 , India,;University of. Illinois in 1988 and Distinguished Faculty of Georgia Tech in 2002

He is a member of NAE in USA. And NAE in India and IEEE, IMAPS and Am Ceramic Society Fellow, and President of IEEE CPMT and IMAPS Societies. He has been a consultant and advisor to many of Fortune 500 semiconductor and systems companies

IEEE recently named him as the father of modern Packaging and created a technical field award in his name—IEEE Rao Tummala Electrronics Packaging Award’