Dr. Yang Cheng
Biography
Dr. Yang has 20 years’ of experience in electronics system and IC packaging development. At present he is senior director of advanced packaging and SiP design at JCET. Before joining JCET, he was at Flex on SiP products and technology development in IoT, automotive, medical, and industrial applications, covering design, manufacturing, and testing areas. He has worked at Intel on memory packaging design and technology development for 13 years. Dr. Yang hold a Ph.D. degree from National University of Singapore, EMBA from Washington University in St. Louis, and Master and Bachelor from Shanghai Jiaotong University.
Company Profile
JCET
JCET Group is the world’s leading integrated-circuit manufacturing and technology services provider, offering a full range of turnkey services that include semiconductor package integration design and characterization, R&D, wafer probe, wafer bumping, package assembly, final test and drop shipment to vendors around the world.
Our comprehensive portfolio covers a wide spectrum of semiconductor applications such as mobile, communication, compute, consumer, automotive, and industrial, through advanced wafer-level packaging, 2.5D/3D, System-in-Package, and reliable flip chip and wire bonding technologies. JCET Group has two R&D centers in China and Korea, six manufacturing locations in China, Korea, and Singapore, and sales centers around the world, providing close technology collaboration and efficient supply-chain manufacturing to our global customers.