The “More than Moore” era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75 mm x 75 mm to 175 mm x 175 mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges for advanced IC substrates. The large package size reduces the number of units per panel, making the panel yield of paramount importance. In addition, with the increasing number of RDL layers, alignment shift per buildup step, due to the process induced substrate distortion can lead to a steady overlay drift and increase the RDL total interconnect length to a point where it exceeds the resistance specification. Solutions to these high value problems will be the subject of this talk.