Chiplet architectures are fundamental to the continued economic viable growth of power efficiency of AI hardware and edge computing. The slowing of Moore’s law has also placed advanced packaging at the critical juncture of technology-architecture intersection driving unique product capabilities. New heterogeneous architectures like 2.5D architectures and 3D Hybrid bonded architectures driving AMD’s industry leading advanced technology roadmap to enable power, performance, area, and cost (PPAC) will be discussed. Other topics including Chiplets for AI, challenges and solutions for large chiplet modules etc. will also be discussed.