As processor complexity has skyrocketed through the 10B transistor mark on the back of sub-10nm technologies, product developers noticed the outgoing defect rates were impacting end-product quality. To maintain acceptable quality, new test insertions like system level test and active burn-in were added to traditional ATE- based sort and packaged test. Initially a high-volume phenomenon in PCs and smartphones, additional known good die insertions have been added, as multi chip devices have become the norm for AI-enabling servers, resulting in a complex set of unique insertions, each with its own development investment, test limits, and data management. In this session, we’ll discuss how connecting insertions together and enabling test migration across a range of insertions, from wafer to SLT to PCB/product test, offers the opportunity to optimize processes for the desired outcome, whether it be time to market, quality, or cost.