27-28 August 2025
Suwon
2-3 December 2025 - Tokyo
For your reference, here’s the line up from last year. We’re working hard at finalizing this year’s speakers. Stay tuned for updates!
Director, IT Div
Day 1 / 08:30 - 08:55
Two years have passed since the formulation of the Semiconductor and Digital Industry Strategy in June 2021, the Ministry of Economy, Trade and Industry revised its Semiconductor and Digital Industry Strategy in June 2023.
In this strategy, in the semiconductor sector, Japan aims to achieve total sales of 15 trillion yen or more for domestic semiconductor manufacturing companies by 2030, and while step 1 is developing semiconductor manufacturing capability, step 2 will bethe establishment of manufacturing technology for 2nm and beyond logic semiconductors. Finally, it will work on the development of future, game-changing technologies, such as photonics-electronics convergence in step 3.
In this presentation, specific initiatives such as research and development, human resource development, and international collaboration based on the Semiconductor and Digital Industry Strategy will be explained, along with the latest policy trends.
Director, IT Industry Division, Commerce and Information Policy Bureau, METI(Ministry of Economy, Trade and Industry)
1998 Joined the Ministry of International Trade and Industry (MITI)
2007 Visiting Scholar, Stanford University
2008 MBA from EDHEC Business School, France
2009 Industrial Revitalization Division
2011 Policy Planning and Coordination Division, Minister’s Secretariat
2014 Japan Economic Revitalization Bureau, Cabinet Secretariat
2016 Deputy Director, JETRO Los Angeles Office,
Director, Industry Creation Policy Division, Principal Director, IT Industry and Digital Economic Security, etc
2021 Counselor for Information Industry and Digital Economy and Security, Minister’s Secretariat
July 1, 2022 Current Position
Senior Managing Executive Officer, Silicon Technology Division, IEEE Fellow
Day 2 / 08:45 - 09:10
As the miniaturization of advanced logic processes continues, the time from design to commercialization is lengthening.
This is due to the increasing difficulty of the manufacturing process, design, and verification associated with the growing complexity of device structures. However, LSIs, such as processors and accelerators for AI, are evolving at a rapid pace and must be commercialized in a short period of time to meet time- to-market requirements. We will introduce the Rapidus model, which solves this problem and achieves short TAT manufacturing.
Joined Toshiba, Semiconductor Device Engineering Labs. in 1988 and engaged in development of advanced SRAM/Logic technologies. 2006-2010: engaged in development of 32nm~20nm CMOS platform technologies with IBM as Toshiba’s representative (VP of R&D). 2013 Senior Manager of Advanced Memory Technology Development Dept. 2022 Director of Memory Technology R&D Center. Joined Rapidus Corporation in April 2023.
Senior Managing Executive Officer, 3D Assembly Division
Day 1 / 09:30 - 09:55
The advancements in semiconductor manufacturing and packaging technologies are revolutionizing the semiconductor industry. Splitting a SoC chip into individual chips by function brings improved yields, shorter design, development cycles, and cost reduction. However, packaging structures are becoming more complex, leading to increased design complexity. To overcome these challenges, the entire industry should promote the integration of front-end and then back-end processes and establish a chiplet ecosystem.
Education: Osaka Univ. Osaka, Japan Bachelor 1986
Graduate School of Osaka Univ. Osaka, Japan PhD 2012
Dr. Yasumitsu Orii joined IBM Japan in 1986 and was a leading expert on Flip Chip organic packages, which had contributed to the performance improvements and miniaturization of such products as servers, laptop computers, and HDDs. The packaging technology is becoming more important for next generation server products as Moore’s Law reaches its limits. His flip chip expertise extended into many related areas. Initially, he was a pioneer of flip chip on FPC (Flexible Printed Circuit) for HDDs, which allowed the read/write amplifier ICs to be mounted on the suspension and much closer to the GMR head. Later, he developed the C2 (Chip Connection) technology that supported low-cost 50-μm-pitch flip chip bonding for the commodity consumer electronics market and it was licensed to a company in Taiwan. At IBM Research Tokyo, he was leading the next generation flip chip organic package, 3D-IC projects and Neuromorphic Computing for IBM Servers and creating new technologies under a Joint Development Program involving many leading Japanese materials companies. He left IBM in 2014 and joined NAGASE & CO., LTD. He established “New Value Creation Office” under the direct control of the president and launched the material informatics software as a service in 2020. He left NAGASE and he joined Rapidus Corporation in 2022/Dec. Now he is the senior managing executive officer to lead the 3D Assembly Division.
Chairman of the Board
Formerly CVP of Intel
Day 1 / 09:00 - 09:25
Advanced packaging is enabling unprecedented levels of product performance as logic and memory chiplets are connected in unique architectures merging back-end silicon fabrication with package assembly. To meet future scaling, high speed signaling and power delivery needs, the package substrate must evolve beyond the capabilities offered by organic substrates. Glass substrates contain the
mechanical, physical and optical properties that allow for more transistors to be delivered in a package, providing better scaling and enabling the assembly of larger chiplet complexes. Intel is driving glass substrate technology and supply chain for advanced packaging solutions and plans to deliver this breakthrough innovation to the market in the second half of this decade.
Dr Hamid Azimi, formerly Corporate VP, Director of Substrate Packaging TD of Intel. He was responsible for advanced substrate packaging for all Intel logic products across substrate suppliers’ factories, as well as the company’s two internal substrate R&D factories. These R&D factories are the birthplace of panel level die embedding technology and play a crucial role for enabling EMIB, the key technology to Intel’s data-centric business and heterogenous packaging. His team works with equipment, material, chemical and substrate suppliers to develop Si-fab backend-like technologies for panel level advanced packaging, and transfer technologies to Intel supplier factories to meet the demand of future Intel products.
Established in 2010, the International Semiconductor Industry Group (ISIG) is a prestigious and trusted global platform, known for fostering collaboration and driving innovation across the semiconductor industry. With a strong foundation through its International Semiconductor Executive Summits (I.S.E.S.), ISIG orchestrates influential regional summits across the U.S., Middle East, Europe and Asia, fully endorsed by local governments and leading companies throughout the semiconductor supply chain.
At ISIG, we are more than just event organizers—we serve as a catalyst for shaping the future of the semiconductor industry. Through high-level executive recruitment, expert consultation, and strategic investor engagement, ISIG empowers global collaboration, helping industry leaders connect, collaborate, and innovate. Our vision is to create a trusted network that transcends borders and disciplines, uniting government officials, academic experts, and investors to tackle the most pressing challenges and seize the greatest opportunities in the semiconductor ecosystem.
Together, we ensure the semiconductor industry remains at the forefront of technological advancement and economic growth, shaping a sustainable future for the global market.
Senior Vice President Business Development & Sales
Day 2 / 11:15 - 11:40
Semiconductor technology has caught the spotlight of global attention, as it is now understood by a broader community and political leaders to be the driving and enabling force for our wealth and wellbeing in the decades to come. It enables progress in communication, entertainment, economy, our life. How to further guarantee prosperity?
Our industry has developed itself over the past decades in a unique, networked and distributed chain of innovation stakeholders, ranging from system houses, ic makers, equipment and material companies and broader supply chain companies, in various continents, which probably is the enabler for the formidable growth and proliferation into essentially all markets.
Success will come through trusted relationships amongst innovators, smart R&D alliances, efficiently bringing together expertise and infrastructure, to meet the required pace of innovation.
Imec has been driving a unique, global, collaborative R&D innovation model over the past 4 decades, building around the opportunities that Moore’s law has been depicting, and further pathfinding to secure healthy roadmaps for our industry in the years to come.
In this talk, we will highlight how imec’s collaborative model can not only be an inspiration, but more so bring key partnering value when aiming for efficiency and global impact on the semiconductor industry. Japan has taken essential investment steps in defining its path for the future, in such collaborative spirit with other continents, aiming for a better world. As proud partners in this ecosystem, we’ll address the challenges on our joint path for success.
Lode Lauwers is Senior Vice President Business Development and Strategy in IMEC, the nanoelectronics R&D Center in Leuven, Belgium. His current focus is to architect new global R&D collaborations and related business models, in line with semiconductor technology initiatives in various continents currently in conception. In that role he also guides imec’s Corporate Business Development strategies in nanoelectronics. Since he joined IMEC in 2005, he had various leading roles in IMEC’s technology business development and partner relation management. He has been driving over 2 decades the build-out, growth and business foundations of imec’s flagship core program with leading IC manufacturers, foundries, equipment and material suppliers and design and system houses. Earlier, he has been general manager of an ASIC design house, part of a US-based ASSP provider for the telecom industry, and scientific advisor for government funding in local and European cooperative networks in micro-electronics and telecommunications. He has a PhD in Electrical Engineering from KU Leuven.
Imec is a world-leading research and innovation center in nanoelectronics and digital technologies. Imec leverages its state-of-the-art R&D infrastructure and its team of more than 5,500 employees and top researchers, for R&D in advanced semiconductor and system scaling, silicon photonics, artificial intelligence, beyond 5G communications and sensing technologies, and in application domains such as health and life sciences, mobility, industry 4.0, agrofood, smart cities, sustainable energy, education, … Imec unites world-industry leaders across the semiconductor value chain, Flanders-based and international tech, pharma, medical and ICT companies, start-ups, and academia and knowledge centers. Imec is headquartered in Leuven (Belgium), and has research sites across Belgium, in the Netherlands and the USA, and representation in 3 continents. In 2021, imec’s revenue (P&L) totaled 732 million euro.
Further information on imec can be found at www.imec-int.com.
Senior Vice President and Chief Technology Officer
Day 2 / 09:15 - 09:40
The semiconductor industry is in the midst of a paradigm shift together with its applied systems triggered by digitalization accelerated by AI technology evolutions in all the systems like evident trends of electrifications and SDV (Software Defined Vehicle) in the automotive industry. As the magnitude and complexity of its applied systems grow exponentially, semiconductor solutions need to integrate more, execute faster with less power, and realize users much better development productivity. Renesas believes the challenge is resolved by building system-oriented solutions for integrations and improving UX (User Experience) values like easier to develop for users. The keynote speech addresses Renesas’ attempts with innovative technologies like chiplet and digitalization/virtualization for system development environment.
Mr. Yoshioka serves as the Senior Vice President and CTO at Renesas. He was appointed to these roles in August 2019, from his experience and technological expertise of the products and the market following the years he has dedicated to Renesas.
He began his career in Hitachi, Ltd in 1986. Since Renesas Electronics Corporation was established in 2010 based on Hitachi, Mitsubishi Electric, and NEC Electronics, he has held many key roles, such as the Vice President of Automotive Control and Analog & Power Systems Business Division, Safety Solution Business Division, and the Senior Vice President of the Automotive Solutions Business Unit.
He has a Bachelor of Engineering degree in Applied Physics from the University of Tokyo and graduated from Stanford University with a Master of Science in Electrical Engineering.
Renesas Electronics empowers a safer, smarter and more sustainable future where technology helps make our lives easier.
A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live.
Senior Fellow Advanced Packaging
Day 1 / 11:30 - 11:55
In the high-performance computing segment, we continue to see an explosion in demand for computing fueled by the proliferation of AI, 5G and edge computing. However, the slowing of Moore’s law has made it challenging to support this demand with traditional monolithic processors. The advent of large language models is also driving a significant demand for memory and high bandwidth interconnects between the compute and memory chips. Chiplet architecture provides a solution to meet the insatiable demand for compute and memory. By creating custom, modular chiplets and integrating heterogeneous architectures on to one package the overall performance of the processor can be enhanced. Advanced packaging technology such as 2.5D and 3D packaging provide solutions to improve the energy efficiency of the interconnects.
In this talk we will dig deeper into the compute and memory demand for AI accelerator chips. We will review AMDs latest innovations on leveraging 2.5D and 3D packaging to drive performance enhancement and energy efficiency. We delve into the design, process co-optimization needed to achieve higher performance while controlling costs and power consumption. We will conclude our talk with a summary of opportunities and challenges that lie ahead.
Deepak Kulkarni is a Fellow, Advanced Packaging at AMD. Deepak has over 15 years of experience in packaging technology development. Over the years, he has held several leadership positions driving substrate technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds 17 patents and nineteen publications on various aspects of packaging such as 2.5D/3D architectures, DFM/DFY and AI techniques applied to yield management. His contributions to the semiconductor industry have been recognized by an Intel Achievement Award, Next 5% award (AMD) and best paper award (ITHERM). Deepak holds a PhD from the University of Illinois Urbana-Champaign with a major in mechanical engineering and a minor in computational science.
For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.
Director of New Technology & System Integration, Advance Packaging and Test
Day 1 / 10:00 - 10:25
The focus of this presentation is on the latest 3DFabric technology innovations for AI and high-performance computing.
The development trends and future applications will be introduced, along with the integrated challenges faced by advanced packages. These challenges include CPI challenges with evolved advanced Si technology, large CoWoS® integrated challenges, design standard and testing integration, and 3DFabric manufacturing complexity.
Kathy Yan, currently Director of New Technology & System Integration, Advance Packaging and Test at TSMC. She is now in charge of new CoWoS-R organic interposer technology RD development for high speed HPC application, advanced packaging mechanical and thermal simulation & validation. She has been also managing new product co-development projects for system customers, across multiple packaging architecture including InFO POP, InFO-SOW, CoWoS-S and CoWoS-R. In addition She is the key player in TSMC 3D Fabric Alliance as the Memory Eco-system program owner. Prior to joining TSMC, she spend most of her career at Intel Advanced packaging RD and Medtronic technology Center in Arizona, US. She has a PhD in Electrical Engineering and Master in Material Science from Auburn University.
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
TSMC deployed 288 distinct process technologies, and manufactured 11,878 products for 522 customers in 2024 by providing the broadest range of advanced, specialty and advanced packaging technology services. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.
SVP Asia
Day 1 / 14:00 - 14:25
I`ll give an overview about NPU landscape
a) geographical view of AI based semiconductor, NPU IP companies
b) funding situation of AI based semiconductor, NPU IP companies (geographically , application)
c) the role of NPU in AI based applications
d) type of NPU usage
e) Automotive AI based semiconductor situation
f) critical points in term of embedded NPU usage
Axel Bialke is SVP Asia of aiMotive which is the AD/ADAS development center of Stellantis as well as CEO of Cross Border Technologies. He has a 40 year track record in Semiconductor and Automotive industry in Asia and Europe and is based in Japan. He is specialized in AI technologies, system architecture for self driving cars, recognition technologies, datasets for AD/ADAS, sensor technologies and Sensor simulation as well as semiconductors for AI applications (NPU technologies). His networks extends to all automotive OEMS, TIER1 and semiconductor company worldwide.
aiMotive was established in 2015 and is based in Budapest ( Hungary ). It has 250 employees and also officies in Japan and US. aiMotive has developed several AI-based technologies for use in AD/ADAS applications. 2022 it was acquired by Stellantis and is now the AD/ADAS development center of Stellantis and also looking into the merger of AD/ADAS and IVI. aiMotive is also selling several technologies under it s own brand on the open market.
Stellantis is one of the largest automotive OEM`s worldwide. aiMotive has developed several technologies for AD/ADAS application
a) Simulator for validation of AD/ADAS application
b) NPU technologies for AI semiconductor
c) Technologies for real and virtual data generation
Sr. Manager Wirebond/Power BU Power
Day 2 / 13:10 - 13:30
When talking about the power semiconductor market, most outsiders would describe it with words like “mature”, “stable” and “simple” compared to the mobile and digital semiconductor markets. One look from the inside will tell you this is not true. With the continued adoption of Wide Band Gap (WBG) materials along with the market forces driving electrification and renewable energy, you will see that power is anything other than “simple”.
Power semiconductors are becoming increasingly important in the overall semiconductor supply chain and innovations need to keep pace with the need for clean, efficient, and higher power delivery. Although innovations in power generally follow the smaller/better/faster/cheaper engine that continues to drive the semiconductor industry, some interesting dynamics are depending on the application and target market. The traditional market wants to standardize, and the new applications value optimization. These competing forces can create havoc from a supply chain standpoint, and as the power semiconductor market trends towards increasing complexity, then manufacturing strategies will need to adapt. From an OSAT perspective, this presents both a challenge and an opportunity.
This presentation will discuss three key areas of the market from an OSAT perspective and look at lessons learned from past events in our industry to give us some insight into what the supply chain might look like as both WBG devices and power foundry services continue to grow with demand from automotive, industrial, compute and commercial applications.
Since joining Amkor Technology in 2020, Katsumi has demonstrated his expertise through various roles within the Power Product Business Unit in Japan. As a dedicated product manager, he has played a pivotal role in the development of power products for diverse clientele in both Japan and international markets. With 22 years of experience in product engineering, development, marketing, planning, and project management within the power device industry, Katsumi brings a wealth of knowledge to his current position. He holds a Bachelor of Science degree in Information and Communication Engineering from a university in Miyagi, Japan.
Amkor Technology, Inc. is the world’s largest US headquartered OSAT (outsourced semiconductor assembly and test). Since its founding in 1968, Amkor has pioneered the outsourcing of IC packaging and test services and is a strategic manufacturing partner for the world’s leading semiconductor companies, foundries, and electronics OEMs. Amkor provides turnkey services for the communication, automotive and industrial, computing, and consumer industries, including but not limited to smartphones, electric vehicles, data centers, artificial intelligence and wearables. Amkor’s operational base includes production facilities, product development centers and sales and support offices located in key electronics manufacturing regions in Asia, Europe and the United States. Learn more at https://amkor.com
CEO, Business Group AP
Day 1 / 12:25 - 12:35
With the slowdown of Moore’s law, Advanced packaging (AP) and heterogeneous integration (HI) has become key and integral to enabling the AI era. As value migrates from wafer fabrication towards packaging, we see a strong inflection point in AP/ HI units’ growth.
Advanced packaging and heterogeneous integration are innovative techniques used in semiconductor technology to enhance the performance, density, and functionality of integrated circuits.
Advanced packaging refers to the diverse set of techniques used to package and interconnect integrated circuits and other components within a single package. These techniques allow for higher performance, reduced form factor, and improved thermal management in electronic devices. Some examples of advanced packaging include 2.5D/3D packaging, fan-out wafer-level packaging, and system in package.
Heterogeneous integration involves combining different semiconductor technologies, such as logic, memory, and sensors, from various sources into a single package. This approach facilitates the creation of more complex and specialized integrated circuits, leading to improved power efficiency, performance, and reduced manufacturing costs.
Both advanced packaging and heterogeneous integration play crucial roles in enabling the development of more powerful and versatile AI electronic devices, and they shall continue to shape the future of semiconductor technology in the foreseeable future.
ASMPT is uniquely positioned to offer total end to end interconnect solution in the highly complicated field of Advanced Packaging and Heterogeneous Integration to our partners, covering the full spectrum of substrate interconnect, wafer laser singulation, 1st level interconnect and 2nd level interconnect.
LIM Choon Khoon (CK) is a Senior Vice President and Chief Executive Officer of Semiconductor Solutions Advanced Packaging (AP).
CK’s career spans key engineering, manufacturing, and regional functional and global general management roles with several global semiconductor companies. As Chief Executive Officer of the Segment’s AP Business Group, he helps provide the industry’s leading first-level interconnect technologies covering leading AP First Level Interconnect (FLI) technologies for logic, HBM, Si Photonics & Co-Packaged Optics, wafer die singulation solution for advanced fabricated wafers and Panel ECD for fine Line/Space organic and glass substrate & Wafer PVD, that are well-positioned to serve and to scale with the most demanding AP needs.
CK holds a Bachelor of Science (Honours) in Production Engineering and Production Management degree from the University of Nottingham, United Kingdom
ASMPT, founded in 1975, is headquartered in Singapore and is listed in Hong Kong Stock Exchange since 1989.
ASMPT is the only company in the world that offers high-quality equipment for all major steps in the electronics manufacturing process – from carrier for chip interconnection to chip assembly and packaging to SMT. No other supplier offers a comparable range and depth of process expertise.
Semiconductor Solutions Segment Business of ASMPT offers a diverse product range from bonding to molding and trim & form to the integration of these activities into complete in-line systems for the microelectronics, semiconductor, camera modules, advanced packaging, photonics, and optoelectronics industries.
The group has successfully established itself as the leading player in the back-end assembly and packaging market with its innovative solutions and constant focus on customer value creation.
President, Entegris Japan
Dr. Koukou Suu graduated and received Ph.D degree in Engineering from Tohoku University, Japan in 1988 and 1993 respectively. He joined ULVAC, Inc. in 1993 and since then has been leading and engaging with developments of numerous semiconductor and electronics technologies including emerging non-volatile memories, high-K capacitors, LED, power devices, thin-film Li-battery as well as 3D packaging manufacturing technologies. He was General Manager of Institute of Semiconductor and Electronics Technologies of the company from 2008 to 2014. Currently he is Executive Officer and Senior Fellow of ULVAC, Inc. as well as President and CEO of ULVAC Technologies, Inc, a company representing ULVAC in North America. He is also an Adjunct Professor of Shanghai Institute of Microsystem and Information Technology of Chinese Academy of Science as well as an Adjunct Industrial Professor of University of South Australia.
Entegris, Inc. is a leading supplier of advanced materials and process solutions for the semiconductor, life sciences, and other high-tech industries. With over 50 years of expertise, we solve our customers’ most demanding challenges through innovative product development and a comprehensive portfolio, grounded in:
– Materials science and analytics
– Microcontamination control
– Advanced materials
– Manufacturing excellence
With a global team of 8,000 employees and ISO 9001-certified facilities, we operate worldwide to support innovation and reliability. Our German and French offices play a key role in Europe’s semiconductor ecosystem, offering proximity and local expertise.
Sustainability is embedded in everything we do. From enabling the desalination industry to regenerating gas purifiers for semiconductor manufacturing at our German facility, we are committed to creating solutions that drive innovation while supporting a more sustainable future for our planet.
Facing material issues, yield challenges, or reliability concerns? Entegris is your trusted partner.
• Filters that purify process gases, fluids, and the ambient fab environment
• Liquid systems that dispense, control, analyze, or transport process fluids
• Gas delivery systems that safely store and deliver toxic gases
• Advanced liquid, gaseous, and solid precursors for chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes
• Advanced materials for wafer surface preparation and integration (SPI) and other processes requiring high purity chemistries
• Specialty chemicals including organometallic and organosilane materials used in semiconductor device manufacturing, monomers and polymers used in the manufacture of medical devices, and isotopically labeled materials used in clinical diagnostics
• Polishing pads for chemical mechanical planarization (CMP) applications
• Slurries for CMP applications and for polishing other substrates including ultra-hard surfaces like silicon carbide (SiC) and gallium nitride (GaN)
• Single-use assemblies for purity and reliability in storage, freezing, and shipment of biopharmaceutical products
• Specialty coatings that provide high-purity surfaces for wear resistance, corrosion protection, and smoothness
• Premium graphite and silicon carbide for high-performance applications
• Shippers and trays for protecting and transporting medical device and disk drive components
• Microenvironments that protect semiconductor wafers and reticles from contamination and breakage
• Cleaning solutions for e-chucks, probe cards, and test contactors
Professor by Special Designation
Day 1 / 15:00 - 15:25
Dr. Nahomi Aoto is working at Hiroshima University as Professor by Special Designation and at Tohoku University as Visiting Professor by Special Designation, from August 2023 after she retired from Micron. She specializes in workforce advancement of university students and younger students, especially women, to attract them to semiconductor technology areas. Before university Dr. Aoto had served semiconductor industry from 1983 to 2023 and contributed to process R&D. She worked for NEC, Elpida Memory, Micron Memory Japan and Micron Technology as a researcher/engineer, manager, Sr. director and officer. In 2019 – 2023, Dr. Aoto focused on building good relationships between students/university and semiconductor industry by giving lectures and speeches, and inspired students to work for semiconductor technology and industry. She had also led women leadership program of Micron until her retirement. Dr. Aoto was chosen as one of four final nominees of 2020 Rising Women of Influence Award of Global Semiconductor Alliance (GSA).
CEO
Day 1 / 12:40 - 13:00
The development of 3D stacking wafer-on-wafer(WoW) technology can provide a large number of connections between the SoC and memory chip, enable solutions for the memory bandwidth and power consumption issues.
AI applications have gradually moved towards the transformer architecture and the model size has also grown to billions of parameters after the launch of ChatGPT at the end of 2022. The increase in model parameters incur the requirements on high memory bandwidth and low power consumption.
WoW hybrid bond technology stacks Logic+Memory wafers together, and provide up to 1ES connections per millimeter square, which is much higher than the thousands of connections using traditional micro bump approach, significantly increase the memory bandwidth between chips. And also, hybrid bond embodies much shorter signal distance between chips, which in turn save lots of data movement power.
Present:
Experienced:
JSMC Holdings is one of the worldwide leading foundry manufacturers that provides customized total solutions and stable supply chain for automotive, communication, AI, and industrial related products with broad range technologies and dedicated services.
Executive Vice President and Chief Strategy Officer
Day 2 / 12:45 - 13:05
The drivers of the semiconductor market have transitioned from a focus on PCs to mobile and now to a data centric “digitalization of everything”, where we are seeing an increasingly diverse end market. While the front-end roadmap is still progressing thanks to EUV lithography and other process technology innovations, it’s no longer sufficient to keep pace with the demand of the new digital society. Different kinds of semiconductor innovation are required to support a diversified end market.
For data center applications, we have seen an acceleration of technical innovations in IC packaging and IC substrates to complement front end wafer fabrication technologies and meet performance, power, and cost requirements.
Heterogeneous integration is actively being implemented with several new 2.5 and 3D architectures, where many integrations are utilizing advanced IC substrates. With interconnect geometry scaling, we see the need and the opportunity to bridge process equipment and process control methodologies across the three worlds of front end, packaging, and substrates.
KLA is partnering with key industry players to bridge these three worlds and this presentation will show the challenges we are facing and problems we are solving to advance the semiconductor technology roadmap for advanced applications like data center.
Similarly, the automotive industry is also experiencing semiconductor innovation as it continues its secular shift towards more electrification, computing, and automation. The introduction of wide bandgap (WBG) materials, like silicon carbide (SiC), have proven to be essential to the proliferation of electric vehicles because of their improved power efficiency over silicon.
WBG power manufacturers are facing significant yield challenges while ramping production to meet industry’s skyrocketing demand. Low yield is impacting both fabrication costs and product reliability and can pose a serious threat to the EV adoption in the market.
This presentation with step through the manufacturing process for SiC power devices to highlight key challenges. From the substrate and epitaxy processes, through device fabrication, wafer singulation, packaging and final test, there are opportunities for optimized processes, advanced process control and inline screening methodologies to improve both reliability and yield.
Keywords: Innovation, Advanced Packaging, Technology Roadmap, Heterogeneous Integration, Substrates, Electrification, Yield, Reliability, Inline Screening, Silicon Carbide
Oreste Donzella serves as Executive Vice President and Chief Strategy Officer at KLA Corporation, leading key corporate growth initiatives and working closely with external stakeholders, such as financial investors and end customers in the broad electronics ecosystem.
Prior to his current role, Oreste was Executive Vice President, managing the Electronics, Packaging and Component (EPC) business group at KLA Corporation, which included multiple product divisions, targeting growth opportunities in specialty semiconductors, packaging, printed circuit board and display markets.
Previously, Oreste was the Chief Marketing Officer (CMO) of KLA. In this role, he oversaw corporate marketing activities, market analytics and forecast, and companywide collaborations with the broad electronics industry.
In the years before his CMO role, Oreste led the world-wide field applications engineering team, and was responsible for Customer Engagement projects and product portfolio optimization for wafer inspection platforms at KLA.
Previously, Oreste was Vice President and General Manager of the Surfscan and SWIFT divisions at KLA-Tencor. In these positions, he was responsible for the unpatterned wafer inspection, wafer geometry, and macro inspection business, overseeing new products development, sales, and marketing activities, customer support, and ultimately, division financial performance (P&L).
Oreste brings 30+ years of experience in the semiconductor industry. Prior to joining KLA in 1999, he spent almost seven years at Texas Instruments and Micron Technology, holding engineering and management positions in the process integration and yield enhancement departments.
Oreste holds various patents and is featured in several technical publications.
In 2020, Oreste was awarded with VLSI Semiconductor All Star for “charting KLA’s path into new markets related to More than Moore semiconductor technologies”
Oreste earned his master’s degree in electrical engineering from the University La Sapienza in Rome, Italy .
KLA develops industry-leading equipment and services that enable innovation throughout the electronics industry. We provide advanced process control and process-enabling solutions for manufacturing wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. In close collaboration with leading customers across the globe, our expert teams of physicists, engineers, data scientists and problem-solvers design solutions that move the world forward. Additional information may be found at kla.com
President Japan
Day 1 / 15:00 - 15:25
Ken Shibata has been immersed in the semiconductor industry since 1980. He initiated his career at a manufacturing company within Hitachi Semiconductor Division, where he spent the first decade as a backend assembly process engineer. Over the subsequent 10 years, he played a pivotal role in promoting the OSAT business. From 2001 to 2014, Ken contributed significantly to Amkor Technology Japan, ultimately holding the position of Representative Director and Sales VP. Following this, he served as Representative Director and Senior Vice President at UTAC Japan from November 2014 to June 2019. Ken joined ISES on October 15, 2023.
Corporate Vice President DRAM Process Integration and Device Technology
Day 2 / 10:45 - 11:10
We present the advancements in DRAM technology that have allowed us to enter the Artificial Intelligence (AI) Era. AI systems and applications have a high demand for memory and storage, which can result in high energy consumption if the technology follows the current scaling law. Therefore, to meet the high memory density, speed, and energy efficiency requirements for demanding AI workloads, we need to innovate High-Bandwidth-Memory (HBM), Processing-in-Memory, 3D DRAM, and Wafer Hybrid boding technology. These innovations require new materials for novel cell structures, new equipment for process development, and Extreme Ultra-Violet (EUV) technology for scaling. Micron is leading the way in developing and delivering energy-efficient products across portfolios and driving supply chains for advanced memory technology, enabling us to deliver breakthrough innovations to the market.
Shigeru Shiratake is the Corporate Vice President for Technology Development’s DRAM and Emerging Memory research development organization. Shiratake joined Micron in 2013 as the Section Director of the DRAM process integration organization. Prior to joining Micron, Shiratake was an executive of Elpida Memory (acquired by Micron in 2013) between 2005 – 2013, leading several DRAM programs. Shiratake experience spans 35 years in the memory technology sectors, and includes additional leadership positions with Renesas Technology Inc., and Mitsubishi Electric, Corp. Shiratake is a published author of many technical papers, holds dozens of patents pertaining to semiconductor technology.
Micron is a world leader in innovative memory solutions that transform how the world uses information. For over 40 years, our company has been instrumental to the world’s most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications.
Senior Analyst
Day 1 / 16:30 - 16:55
The semiconductor industry is likely to take unprecedented growth in the future.
Main driver of the semiconductor industry has been personal consumption to stimulate PC/TV/Smart phone, but from now on, government investments, such as DX/GX, will be added to the semiconductor driver.
In addition, the use of generative AI will revitalize the market for massive servers and communication equipment.
Regional Account Business Unit
Day 1 / 12:00 - 12:20
Previous waves of growth experienced by the semiconductor ecosystem were dominated by the onset of the personal computer, followed by the arrival of internet, and then the smartphone – the next wave of growth is going to be largely dominated by the demand for AI enabled device technologies. Whether in Automotive, Industrial or Consumer applications, the demand for AI technologies cuts across multiple segments of the semiconductor industry from advanced node next generation CPU/GPUs to advanced high bandwidth memory, chiplet technologies drawn from a variety of mature and specialty node device technologies to finally, advanced packaging at both the wafer and panel levels. This presentation will introduce Onto Innovation and in discussing the many challenges faced in supporting waves of end market growth enabled by advanced technologies such as AI or enabling specialty technologies such as Power in Automotive and Green Energy, it will highlight the many unique and powerful process control technologies Onto is bringing to the semiconductor market.
Toshihito Tsuga is General Manager of the Regional Account Division. He joined Onto Innovation Japan (Nanometrics Japan) in 2019 as Sales Manager. Prior to joining Onto Innovation, he was Product Manager at KLA Japan from 2005 to 2019. Tsuga has over 30 years of experience in Semiconductor industry, including at IC device makers as process engineer at Texas Instrument Japan, Renesas Technology Inc.,. Tsuga received ph. D degree from Tohoku University.
Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.
General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com
CTO, Semiconductor Materials, Resonac Holdings Corporation
Day 1 / 17:00 - 17:30
Hidenori Abe CTO for semiconductor materials, Resonac Holdings Corporation Executive director, Electronics Business Headquarters, Resonac Corporation. He is leading electronics materials R&D and strategy for semiconductor, substrate and display. Until 2023, he was the head of Electronics R&D Center and Packaging Solution Center, which is open innovation hub in advanced packaging development. I launched JOINT2, new advanced packaging consortium targeting 2.xD and 3D package in 2021.Prior to the above mission, he have been a General Manager of CMP Slurry Business Sector for three years. Before that he was a Manager of Marketing Promotion Group in Innovation Promotion Center at Hitachi Chemical (HC) for 2 years. When the career, he was promoted new R&D projects, especially targeting new business field using new technologies, and also to promote developing R&D products. As a side note, HC is one of the merged companies of Resonac. Hidenori Abe was Manager of Business Development Group in Packaging Solution Center at HC for 1 year with responsibility to promote open laboratory to partners such as customers and equipment makers, responsibility of marketing wearable related materials. Before that, he was epoxy molding compounds (EMC) engineer. During his 16 years carrier as engineer, he spent time doing responsibility of development of non-conductive carbon, green EMC, Cu wire compatible EMC, wafer level compression compounds, power module EMC and so on. His Cu wire compatible EMC development work contributed to the promotion to Cu wire conversion through several published papers. He received a master degree in chemical engineering field from Tokyo Institute of Technology, Japan and a master degree at the EMBA course from Oxford, UK.
Resonac defines its purpose as “Change society through the power of chemistry.” Resonac aims to be a world-class functional chemical manufacturer, creating functions necessary for the times, supporting technological innovation, and contributing to the sustainable development of our customers. Resonac is Global Leading semiconductor materials supplier. In order to achieve technological innovation for solving various social issues, it is essential for us to make wide-ranging co-creative efforts with partners, and Resonac is open to collaboration including 1on1 co-development with any partner.
We have opened a Packaging Solution Center and are actively engaged in next-generation semiconductor co-creation activities through JOINT2 with many partner companies. Furthermore, starting this year, we will also seek co-creation opportunities in the United States by launching US-JOINT.
CVP Business Development Team, AVP
Day 1 / 14:30 - 14:55
As the demand for increased data bandwidths and additional functionalities intensifies in AI era, advanced packaging has garnered much interest as a key potential solution. The value of advanced packaging technology lies in enabling heterogeneous integration and chiplet solutions. Advances in heterogeneous chip/chiplet packages are essential for empowering today’s device manufacturers to pursue tomorrow’s breakthroughs. Advanced packaging solutions including FOPKG (FOWLP, FO Panel level packaging) and 3D variations are necessary to keep innovative vibrant.
For high-performance computing (HPC) and AI-edge applicatoins, advanced package has been developed based on a FOPKG, silicon interposer, embedded silicon bridge, or re-distribution (RDL) interposer integrating multiple logic devices, including chiplets and memory. This allows for a higher data transfer system capability. The next-generation heterogenous integrations are based on chiplet technology, where logic or memory dies are placed on top of the logic die or vice versa. Further down the line, the combination of wafer level integration, 3D-TSV and interposer technologies will contribute to request to fulfil the needs of ultra-high-performance in data transfer and minimized the system package form factor.
This presentation introduces Samsung’s advanced package platform for AI, mobile and automotive, in terms of echnical challenges, and opportunities for emerging chiplet applications. It also discusses the current activities of advanced packaging and industrial collaboration in the supplychain and ecosystem for further systematic integration and product innovation.
Dr. YOON is currently working as Corporate VP/Head of Group, PKG group, Product Technology, S.LSI, Samsung Electronics. Prior to joining Samsung, He was director of group technology strategy, STATS ChipPAC, JCET Group. He also worked deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Served as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.
Samsung Electronics Co., Ltd. engages in the manufacturing and selling of electronics and computer peripherals. The company operates through following business divisions: Consumer Electronics, Information Technology & Mobile Communications and Device Solutions. The Consumer Electronics business division provides cable television, monitor, printer, air-conditioners, refrigerators, washing machines and medical devices. The Information Technology & Mobile Communications business division offers handheld products, communication systems, computers and digital cameras. The Device Solutions business division comprises of memory, system large scale integrated circuit and foundry. The company was founded on January 13, 1969 and is headquartered in Suwon, South Korea.
CTO and Senior EVP Innovation
Day 1 / 17:00 - 17:30
Christophe Maleville has been appointed Chief Technology Officer and Senior Executive Vice President of Soitec’s Innovation.
He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as vice president, SOI Products Platform at Soitec, working closely with key customers worldwide.
Maleville has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from Grenoble Institute of Technology and obtained an executive MBA from INSEAD.
Soitec is a world leader in the production of innovative semiconductor materials. The company leverages its unique technologies to serve the electronics markets.
In meeting the technical and economic challenges of mainstream electronics, Soitec is helping to speed up the mobile and digital revolutions. Its products are used to manufacture chips that go into smartphones, tablets, computers, IT servers and data centers as well as electronic components in cars, connected devices, and industrial and medical equipment.
With more than 4,000 patents, the company pursues a strategy of disruptive innovation to provide its customers with products that combine performance, energy efficiency and competitiveness.
Soitec is headquartered in Bernin France. The company was founded 30 years ago in Grenoble’s high-tech ecosystem and has manufacturing facilities, R&D centers and sales offices in Europe, the United States and Asia. Soitec is listed on the CAC NEXT 20, in Paris.
For more information visit: www.soitec.com.
Director/Professor
Day 1 / 15:00 - 15:25
Tetsuo Endoh joined ULSI Research Center Toshiba Co. in 1987 and was engaged in the R&D of NAND Memory. He became a lecturer at the Research Institute of Electrical Communication, Tohoku University in 1995. He is a professor at the Department of Electrical Engineering, the Graduate School of Engineering, Tohoku University and director of the Center for Innovative Integrated Electronic Systems (CIES). His current interests are novel 3D structured device technology, such as Vertical MOSFETs; high-density memory, such as SRAM, DRAM, 3D-NAND memory and STT-MRAM; and beyond-CMOS technology, such as spintronics-based non-volatile Logic for ultralow power systems such as mobile systems, AI systems and IoT systems. He is also interested in power-management technology, such as GaN on Si based power devices and power integrated circuits with low energy loss and low power consumption for automotive applications. He received the 14th Prime Minister’s Award for his Contribution to Industry-Academia-Government Collaboration in 2016.
He received 2017 National Invention Award “the 21st century Encouragement of Invention Prize” on June 12th for his contribution of the invent of 3D-NAND Memory technology. He received a 2020 VLSI Test of Time Award, VLSI Symposium, 2021. He was a Fellow of the IEEE from 2023.
The Center for Innovative Integrated Electronic Systems (CIES) has conducted the CIES consortium consisting of industry-academia joint researches, major national projects, and regional collaboration projects from fields such as materials, equipment, devices, circuits and systems through the cooperation of domestic and foreign companies with support of local government. CIES has expanded its R&D field from spintronics to AI hardware and power electronics, and has promoted to develop core technologies related to integrated electronics. To date, the center has developed various innovative technologies with highest performance in the world, has made progress in developing IoT and AI systems that require ultra-low power consumption. In addition, with the establishment of the startup “Power Spin Inc.” from Tohoku University, we are accelerating the development of the innovative technologies that we are developing into social implementation and the further advancement of industry-academia collaboration. In June 2021, Tohoku University established the Tohoku University Semiconductor Technology Co-creation to contribute to Japan’s semiconductor strategy and the world’s energy-saving society. In addition to this co-creation, CIES is positioned as a spintronics low power logic semiconductor development base in Japan’s semiconductor strategy, and is further strengthening efforts for promotion of industry-academia-government co-creation and social implementation. We will continue to create innovative core technologies and contribute to the industry and the enhancement of global competitiveness by the practical applications, and “new creation and innovation” through global and regional partnership.
Professor
Day 1 / 15:00 - 15:25
Kazuaki Sawada was born in Kumamoto, Japan in 1963. He received a Ph.D. degree in system and information engineering in 1991, from Toyohashi University of Technology, Aichi, Japan. Doctor of Engineering.
From 1991 to 1998, he was an Assistant Professor in the Research Institute of Electronics, Shizuoka University, Shizuoka, Japan. Since 1998, He was a lecturer at the Department of Electrical and Electronic Engineering, Toyohashi University of Technology from 1991 to 1998, an associate professor in 2000 and a professor at the Faculty of Engineering, Toyohashi University of Technology since 2007. In 2005, he was a visiting professor at the Technical University of Munich.
Prof. Sawada was Director of the Venture Business Laboratory and Director of the Incubation Facility from 2008 to 2014, Assistant to the university president as a Director of the KOSEN Collaboration Office in 2016, Director of the Electronics-Inspired Interdisciplinary Research Institute (EIIRIS) from 2014 to 2016. He is currently Director of the Institute for Research in Next-Generation Semiconductors and Sensing Science (IRES²) from 2023.
In 2009, he received the 65th Electrical Society of Japan Award for the Promotion of Electric Science (Progress Award). In 2013, he received the Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology (Research Category). His current research focuses on smart sensors that integrate integrated circuit technology and sensor technology. In particular, he is developing non-label bio-imaging sensing devices and multimodal sensors by integrating bio-related technologies and integrated circuit technologies.
1963年熊本県生まれ。1991年豊橋技術科学大学大学院工学研究科博士後期課程システム情報工学専攻修了、工学博士。1991年から1998年静岡大学電子工学研究所助手。同年豊橋技術科学大学電気・電子工学系講師。2000年同准教授。2005年ミュンヘン工科大学客員教授。2007年より豊橋技術科学大学工学部教授。
2008年から2014年 ベンチャー・ビジネス・ラボラトリーセンター長、インキュベーション施設長、2014年から2016年 同大学長補佐 高専連携室長、2016年同大学 エレクトロニクス先端融合研究所(EIIRIS)所長、2023年から現在 同大学 次世代半導体・センサ科学研究所(IRES²)所長。
2009年 電気学会 第65回電気学術振興賞(進歩賞)受賞。
2013年 文部科学大臣表彰科学技術賞(研究部門)受賞。 現在の研究テーマは、集積回路技術とセンサ技術を融合したスマートセンサに関する研究。特に、バイオ関連技術と集積回路技術を融合したノンラベル生体画像センシングデバイスおよびマルチモーダルセンサの開発。
Senior Vice President of Global Backend Operations
Day 2 / 13:35 - 13:55
High Voltage (HV) power semiconductors play a critical role in the mass commercialization of electrical vehicles. Silicon carbide (SiC) based MOSFET’s have become commonplace as a superior alternative to silicon devices in HV applications.
While this shift to SiC devices results in significant attention on wafer substrates, epitaxial layers, and front end technology, it also results in increased focus on backend packaging requirements. Silicon carbide devices run at a higher junction temperature compared to silicon devices, which drives unique packaging trends and roadmaps.
Wolfspeed is leading the transformation from silicon to silicon carbide (SiC), and best-in-class packaging materials, equipment, and processes are needed to unlock the full potential of silicon carbide devices.
Joseph Roybal is the Senior Vice President of Global Backend Operations at Wolfspeed aligning backend manufacturing roadmaps, production strategies, and capital allocation to scale efficiently with Wolfspeed’s exponential growth. He leads an expanding worldwide team focused on systemic manufacturing solutions, SiC package innovation, strategic partnerships with OSATs, and effective product manufacturing solutions for all Wolfspeed businesses and major SiC backend operations.
Wolfspeed (NYSE: WOLF) leads the market in the worldwide adoption of Silicon Carbide and GaN technologies. We provide industry-leading solutions for efficient energy consumption and a sustainable future. Wolfspeed’s product families include Silicon Carbide materials, power-switching devices and RF devices targeted for various applications such as electric vehicles, fast charging, 5G, renewable energy and storage, and aerospace and defense. We unleash the power of possibilities through hard work, collaboration and a passion for innovation. Learn more at www.wolfspeed.com.
Wolfspeed® is a registered trademark of Wolfspeed, Inc.
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