Heterogeneous Integration Enabled by Advanced Chiplet Packaging

ISES Docs:

With the growing demand of high performance IC, heterogeneous system integration of multiple smaller chiplets by advanced packaging technology becomes one of the major driving forces of the semiconductor industry innovation. New technologies in high bandwidth 2.5D and 3D interconnection enable complex designs implementation. Chip-Package co-design is prerequisite to meet the target performance and STCO (system-technology co-optimization) methodology is critical to advance chiplet architecture for optimal system performance.

Dr. Yang Cheng photo

Dr. Yang Cheng

Senior Director Design Service BU

JCET Group Co., Ltd.

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