The hole size can be less than 15 microns, and the metal filling capacity aspect ratio can reach 10:1. It adopts high-density intermediate layer wiring, with a minimum line width and line spacing of less than 1.5um, meeting the needs of high-density interconnections such as high-performance memory and CPU. The entire packaging body uses glass as the core layer of the intermediate layer, and uses the “RDL-First” process to flip the chip onto multiple layers of RDL wiring layers to achieve electrical interconnection. Compared with TSV, it reduces parasitic capacitance and inductance effects, reduces transmission signal delay, and can be widely used in high-frequency transmission fields.