Hybrid Bonding: Innovation to Adoption

Day 1 / 14:05 - 14:15

Hybrid bonding allows semiconductor wafers or individual die to be bonded with exceptionally fine-pitch (scalable to 1 micron) 3D electrical interconnects at low temperature without pressure or adhesives. Hybrid bonding was invented by a company called Ziptronix which was later acquired by Adeia (formally known as Xperi) in 2015. Since then, Adeia has continued to invest heavily in hybrid bonding R&D and supply chain enablement for production worthy wafer-to-wafer and die-to-wafer hybrid bonding processes. Adeia, a pioneer in hybrid bonding, has licensed numerous semiconductor companies to the bonding portfolio including Sony, SK hynix, Samsung, Micron, Kioxia, Western Digital, Qorvo, Canon, LAPIS, and UMC. Several of these companies engaged in a technology transfer program as well. Hybrid bonding technology was commercially adopted in stacked BSI image sensors, stacked 3D NAND memories, logic processors, and is anticipated to be adopted soon in HBM and RF front-end devices. In logic applications, a large die can be disaggregated into separate functions such as cache memory and processor. After disaggregation, the functional chiplets can be bonded on top of a core processor die to create a fully functional circuit. The hybrid bonding technology is a must-have tool to provide a multi-generational roadmap of products in high performance computing devices such as CPU, GPU, FPGA, SoC, other logic, memories, and 3D chiplet integrations.

A 360 View of Semiconductor Test from AI and Security Perspective

Day 1 / 13:45 - 14:05

This keynote will explore the impact of deep learning including large language models on the semiconductor test. We will highlight the opportunities these models present for real-time data processing and discovery of insights, with specific applications in computer vision and natural language processing. However, the use of these models also introduces new security risks, particularly regarding the use of cloud infrastructure for collection of data, training and inference. By examining past attacks on networks, we will discuss the potential for malicious actors to steal data or intellectual property from companies. Attendees will gain an understanding of the opportunities and challenges in AI and security for the coming years and the importance of considering security measures in the development and deployment of these advanced solutions.

Digitalisation of Supply Chain – Using Latest Technology to Improve Logistics

Day 1 / 16:20 - 16:30

For years, the logistics industry has been challenged by its reliance on manual processes from order placement and tracking to delivery.Recent global disruptions such as COVID-19 and labor strikes have made shipping more and more difficult, but Airspace excels in the most challenging circumstances.You cannot rely on traditional logistics anymore.Airspace has built a shipping platform that’s powered by proprietary AI technology. With mobile and desktop functionality, Airspace has offered major companies in the semiconductor industry the most reliable shipping options and full visibility along the way. By calculating millions of routes for you in seconds, your most critical shipments can get there faster and more efficiently than you ever thought possible.

New Energy to Semiconductor – Heterogeneous Integration Packaging

Day 1 / 12:20 - 12:40

Heterogeneous Integration (HI) is now one of key semiconductor worldwide trends and developing important impact and increasing influence to chip designer, Fab, OSAT, OEM/ODM and entire supply-chain enablers. The view on impact and influence can be pretty different to mobile, IoT, HPC, and automotive applications’ system developers based on various HI solutions. This presentation will discuss the HI packaging as a new enabling energy for semiconductor migration.

Challenges and Solution of FLI Technologies in various HI Packaging Architetures

Day 1 / 16:45 - 16:55

“More Than Moore” with heterogeneous integrated Chiplets in different Advanced Packaging Architectures are continuously being developed in our Industry.

Along the development of these Advanced Packaging Architectures with the objectives of delivering the same or even better device performance as if it is in System On Chip (SOC), while at the same time of achieving the best cost of making, it brings challenges to advanced packaging engineer. ASMPT, being the total interconnect solution provider, has determined to collaborate with our customers and partners to overcome these challenges and offer the best-in-class interconnect equipment solutions to address their needs in a timely manner.

ASMPT is aiming to be a Total Interconnect Solution supplier establishing the widest product portfolio in Advanced Packaging Technology, from with thin film interconnect, to first level (die to wafer & substrate) as well as broad level interconnect (package to PCB). I am happy to share more with this presentation.

Unleashing the Power of AI: Opportunities and Challenges Ahead

Day 2 / 13:50 - 14:10

Artificial intelligence (AI) has rapidly become an integral part of our lives, bringing convenience and efficiency to various aspects of work and daily life. This speech will explore the latest AI applications and examine the opportunities they offer. However, as we embrace the benefits of AI, we must also be aware of the potential challenges it poses. We will discuss the risks of workforce displacement, bias, and privacy infringement that come with AI deployment. Additionally, we will examine the environmental impact of AI, with a focus on the energy consumption of model training. We will discuss how the rapid growth of AI model parameters leads to the crossing of energy production and consumption curves, and suggest potential solutions to mitigate the issue. Ultimately, this speech will provide a comprehensive overview of the current state of AI, its opportunities, and its challenges, and offer guidance on how we can navigate this transformative technology.

Opening Speech – Challenges & Opportunities of LLM and Generative AI: A Hardware Perspective

Day 2 / 08:40 - 09:00

Recent advancements in Large Language Models (LLMs) and Generative Artificial Intelligence (Generative AI) have presented an exciting opportunity for developers, as exemplified by ChatGPT, which can mimic human dialogue and decision-making. However, the tremendous computing power and energy consumption required by the hardware implementing these models pose a considerable cost and challenge, due to a huge number of parameters and complex neural network architecture.

This talk will explore the potential of designing more efficient hardware for deployment and inference of large language models, from an integrated circuit (IC) hardware perspective. Possible methods of AI model compression, such as quantization, pruning or knowledge distillation will be covered as well as AI chip design based on Computing-in-Memory (CIM), Deep-Learning Accelerator (DLA) and Chiplets. This talk will also discuss the hardware and software co-design methodology and tools needed for improving the design quality and productivity.

Gala Dinner Sponsored by Onto Innovation

Day 1 / 18:30 - 21:00

Welcome Speech:

Opportunities and Challenges for MicroLED Display

Day 2 / 11:30 - 11:50

Micro-light-emitting diode (MicroLED) display technology has drawn a lot of attention in display industry recently owing to the superior optical and electrical properties. Compared to conventional display technologies, MicroLED display demonstrates higher efficiencies, longer lifetime, much higher brightness, ultra-high pixel density, faster response time and wider color gamut. MicroLED display is an emerging technology which can be used for all current display applications and new scenarios, such as transparent, seamless tiling, and AR glasses for metaverse. Based on our proprietary PixeLED display, SMAR·Tech, PixeLED Matrix, and µ-PixeLED technologies, we could utilize different process for each application with MicroLED displays.

Inspiring a new reality with XR

Day 2 / 09:30 - 09:50

The merge of digital and physical worlds, so called metaverse, is now happening. The metaverse is a vision of digital community. Accessing the metaverse, requires devices that allow users to experience the spatial internet. Qualcomm’s decade-plus investment in XR along with our foundational technologies enables the creation and widespread adoption of XR headsets to revolutionize digital experiences and provide an entry point of choice into the metaverse as it evolves. With the combination of high performance and low power computing, 5G and AI, we believe XR may have a greater impact on our world than PCs and smartphones combined.

From Hyperscale Models to Heterogeneous SoCs: Industrializing Neural Network Deployment with ONNC

Day 2 / 13:30 - 13:50

Large language models (LLMs) have become an increasingly prominent feature in various computing platforms, such as data centers, smartphones, and microcontrollers. As such, their potential applications in both human-to-machine interfaces (HMIs) and machine-to-machine interfaces (M2MI) have been extensively studied and discussed. However, implementing hyper-scale LLMs on heterogeneous multicore System-on-Chips (SoCs) poses significant challenges. In this talk, we will discuss the key challenges, including issues related to hardware/software interfaces, verification, and SoC architecture exploration. At the end of this talk, we will propose a practical workflow and corresponding solutions we’ve applied in many cases. And see how our standard tool – ONNC – is used in the workflow.

3DIC W2W and D2W Hybrid Bonding

Day 1 / 17:05 - 17:10

Replacing traditional solder based micro-bump interconnects with Hybrid Bonding process flows is still considered a game changer for 3D integration. This interconnect method offers a unique solution for contact pitch scaling and therefore is in the spotlight of R&D roadmaps at all major research institutions, IDMs and foundries as well as the equipment and materials industry. In order to ensure optimum overlay results to allow for small interconnect pitches, the best possible alignment accuracy and repeatability needs to be consistently maintained during the joining process. Depending on the specific application there are different processing schemes for Hybrid Bonding which co-exist. These include wafer to wafer (W2W), collective die to wafer (CoD2W) as well as sequential die to wafer (D2W) approaches which all need to be carried out at cleanliness levels that are comparable to front-end-of-line (FEOL) requirements. Each of these process flows comes with specific challenges which need to be addressed from an equipment as well as a process perspective. SUSS MicroTec leverages its leading position in wet processing and precision alignment for wafer level processes and has partnered with SET (Smart Equipment Technology), who is one of the technology leading flip-chip bonder manufacturers. SUSS MicroTec looks back at many years of hybrid bonding co-optimization activities with the research partner imec for collective D2W, while SET has worked for many years with CEA Leti on sequential D2W. Our solutions are optimized based on the learnings from these activities. In order to ensure optimum yield it is essential to monitor the overlay results with no blind spots across the wafer. Therefore a high throughput metrology system has been developed at SUSS MicroTec, which can be used for in-line inspection to trigger control loops and to record quality data for all dies on the wafer. Stand-alone metrology solutions with multiple overlay verification modules allow customers to scale their measurement capabilities according to their manufacturing needs. Specific state-of-the art alignment and overlay results for both, integrated W2W and D2W Hybrid Bonding schemes will be reviewed.

Display Technology for Metaverse – A Foundry’s Perspective

Day 2 / 11:10 - 11:30

In the past decades, glass substrates with emission layers built on top were widely used in all kinds of display devices. Silicon chips played the traditional role as “driver ICs” to control LCD and OLED display panels. For emerging micro display technology in Metaverse applications, Silicon chips are further adopted to provide higher pixel resolution for better user experience. Emission layers on Si substrates (so called “Si-based micro display”) becomes popular for XR applications in Metaverse. There are several approaches to integrate multiple functions of chips within a Metaverse micro display. Pioneer system companies and panel companies work closely with Si foundries to develop high quality, reliable and cost-effective products. Of course, there are still several challenges in system integration and Si technology itself. In this presentation, we will share our thoughts about the role of Si technology in Metaverse micro display applications from a foundry perspective.