27-28 August 2025
Suwon
President & CEO
Day 1 / 08:10 - 08:30
Greater Phoenix is home to an ever-expanding ecosystem of semiconductor manufacturing and its supply chain. Long-term strategic planning of resources at the state and regional level have supported this growth, ensuring that adequate water and nation-leading grid reliability meet the needs of industry. Paired with a robust workforce and an educational system anchored by Arizona State University and the Maricopa County Community College District, the region has the requisite labor force to meet the needs of key industry sectors. Greater Phoenix is a top global destination for businesses and uniquely positioned to seize the momentum of technological innovation and advanced industry to support future development.
Chris Camacho serves as president & CEO of the Greater Phoenix Economic Council (GPEC), one of the longest-standing public-private partnerships for economic development across the country. As chief executive, Chris leads the development and execution of the region’s strategic economic strategy, oversees domestic and international business development, and ensures the market position remains competitive through coordination with partner organizations, private sector leaders, and municipal and state leadership. GPEC has attracted more than 540 companies during his tenure, creating more than 100,000 jobs and $56.8 billion in capital investment. Some notable projects include TSMC, Apple, LG Energy Solutions, Microsoft, GoDaddy, Amazon, Garmin, General Motors, HelloFresh, KORE Power, Williams-Sonoma and headquarters including Benchmark Electronics, Carlisle Companies, Rogers Corporation and EMD Electronics. In October 2021, Chris led GPEC to being recognized as the top economicdevelopment organization globally by the International Economic Development Council a year after being named the top EDO in the U.S. in 2020.
Established in 1989, the Greater Phoenix Economic Council (GPEC) actively works to attract and grow quality businesses and advocate for the competitiveness of Greater Phoenix. As the regional economic development organization, GPEC works with 22 member communities, Maricopa County and almost 200 private investors to accomplish its mission, and serve as a strategic partner to companies across the world as they expand or relocate. Consistently ranked as a top national economic development organization, GPEC’s approach to connectivity extends beyond the fabric of the community. Known as The Connected Place, Greater Phoenix is in a relentless pursuit of innovative and entrepreneurial technology-focused companies that are committed to changing the game. As a result, over the past 32 years GPEC has fueled the regional economy by helping more than 895 companies, creating more than 163,000 jobs and $33.4 billion in capital investment.
CVP, Advanced Packaging
Day 1 / 10:30 - 11:00
Chiplet architectures are fundamental to the continued economic viable growth of power efficient computing. Thus, the criticality of advanced packaging technologies and architectures correlated to Moore’s Law’s next frontier is high. New heterogeneous architectures, along with AMD’s industry leading advanced packaging roadmap, enable power, performance, area, and cost (PPAC). PPAC considerations per product influence the choice of Substrate (2D), Fanout based (2.5D) and Hybrid Bonded (3D) technologies and will be addressed in this keynote. Finally, AMD’s High Performance Fanout previewed in the RDNA3 architecture along with enabling technologies like power delivery and thermal improvements will be detailed.
Dr. Raja Swaminathan is the Corporate Vice President of Packaging at AMD, spearheading the development of AMD’s advanced packaging and heterogeneous integration roadmap. With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan’s expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple’s Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators. Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to their name, Dr. Swaminathan was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology.
For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.
SVP & GM Assembly and Test Technology Development
Day 1 / 08:30 - 09:00
Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. This trend is set to continue as on-package heterogeneous integration of diverse IP from multiple process nodes and multiple foundries will enable new product concepts, decrease time to market and deliver cost/yield benefits. Additionally, novel 3D architectures and continued die-to-die interconnect scaling are opening previously un-achievable concepts for die partitioning and on-package capability integration. These technical challenges are requiring solutions across the ecosystem (Die/Package/Board/System) which provide opportunities for groundbreaking innovation. This presentation will highlight some of the key challenges the industry will have to jointly address to enable the 3D heterogeneous integration future, such as drivers in interconnect scaling, advanced substrate developments, and technologies to enable power and performance gains. A specific example of this is optical on-package integration, where Intel is taking an aggressive approach to enable highly scalable and manufacturable solutions with applicability beyond niche designs.
Dr. Babak Sabi, formerly Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development.
Babak joined Intel in 1984. Prior to leading ATTD, he oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices.
Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.
SVP Technology Development
Day 2 / 08:30 - 09:00
A memory and storage hierarchy evolution is unfolding before us. Homogenous data centers that met our needs in the past, will not meet our future needs.
We must look to heterogenous solutions that require an expansion of the current memory hierarchy, and ultimately, a convergence of memory and storage.
Conventional scaling must continue, while disruptive 3D, and other advanced solutions will emerge to move us into the next few decades of memory advancement.
Advanced Packaging solutions will play a critical role in this expanded hierarchy, but to achieve this monumental shift, the collaboration, knowledge-sharing, and
innovation our industry has relied on to extend Moore’s Law over the past decade must now push the boundaries, to move the packaging supply chain to a front-end like model.
At the same time, we must keep focus on more sustainable and cost-effective solutions while building a strong talent-based workforce to support long-term growth.
We face many near-term challenges to enable this new ecosystem, but if successful, our industry will emerge with a longer-term roadmap that impacts and enriches lives for generations to come.
Naga Chandrasekaran is senior vice president of technology development at Micron Technology. Dr. Chandrasekaran leads Micron’s global technology development and engineering efforts related to the scaling of current memory technologies, advanced packaging technology, as well as investigating emerging memory technology solutions to support Micron’s future requirements. He also manages mask technology development, corporate characterization labs, advanced modeling and data analytics, and R&D fabrication operations at Micron’s headquarters in Boise, Idaho. He was appointed to his current position in 2019.
In 2001, Dr. Chandrasekaran joined Micron as a CMP development engineer and since then has held a series of positions of increasing responsibility in process and equipment development across multiple R&D process areas, leading manufacturing and technology transfer efforts, integration of new business units, and development of solar, LED and display technology. From 2007 to 2008, he also served as fab engineering manager for IM Flash, Singapore Operations. He most recently served as senior vice president of process research and technology development.
Dr. Chandrasekaran has authored several keynote publications and patents, and he has served as an invited panel speaker at several conferences. He has also received several awards, including Jiri Tlusty Outstanding Young Manufacturing Engineer of the Year, awarded by the Society of Manufacturing Engineers in 2003, and Engineering Manager of the Year, awarded by the American Society of Engineering Management (ASEM) in 2018.
Dr. Chandrasekaran earned a bachelor’s degree in mechanical engineering from the University of Madras. He earned both a master’s and a doctorate degree in mechanical engineering from Oklahoma State University and dual executive MBAs from the University of California, Los Angeles (UCLA-Anderson School of Management) and the National University of Singapore.
Micron is a world leader in innovative memory solutions that transform how the world uses information. For over 40 years, our company has been instrumental to the world’s most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications.
President & CEO
Day 2 / 08:00 - 08:30
With the passage and signing of the CHIPS and Science Act of 2022, companies in and adjacent to the semiconductor industry are working on plans to help revitalize domestic manufacturing, develop the workforce, strengthen American supply chains, and accelerate the technologies of the future. During this keynote talk, SkyWater President and CEO Thomas Sonderman will talk about how a company like SkyWater can address the challenges of bringing chip manufacturing back to the U.S., invest in opportunities for supply chain certainty and security and enable nimble new innovations that can be accelerated with CHIPS funding to lead the next wave of computing.
Thomas Sonderman is the president and CEO of SkyWater Technology, a U.S.-owned and operated pure-play semiconductor manufacturer and a DOD-accredited Trusted supplier. He joined SkyWater in 2017 as the lead executive, driving the company’s successful business transformation from an IDM to a pure play foundry. He has effectively diversified SkyWater’s customer base by defining new product markets and target customers while simultaneously improving operational efficiencies. Mr. Sonderman has leveraged SkyWater’s U.S-based manufacturing operations to expand the company’s government business and to focus on reinstating a strong domestic commercial manufacturing presence. He has built a world class leadership team that inspires over 500 employees to deliver process R&D innovation and operational excellence.
Mr. Sonderman’s extensive industry experience in all aspects of fab operations has delivered market leadership and increased shareholder value to high-technology industry leaders Rudolph Technologies, Globalfoundries and AMD. Notably, he played a critical role serving as part of an executive team at AMD that spun-off manufacturing operations to form Globalfoundries.
A widely recognized subject matter expert, Mr. Sonderman is the author of 50 patents and a highly sought-after industry speaker. He received a Bachelor of Science degree in chemical engineering from Missouri University of Science Technology and a Master of Science degree in electrical engineering from National Technological University.
SkyWater (NASDAQ: SKYT) is a U.S.-based semiconductor manufacturer and a DMEA-accredited Category 1A Trusted Supplier. SkyWater’s Technology as a Service model streamlines the path to production for customers with development services, volume production and heterogeneous integration solutions in its U.S. facilities. This pioneering model enables innovators to co-create the next wave of technology within diverse categories including mixed-signal CMOS, ROICs, rad-hard ICs, MEMS, superconducting ICs, photonics and advanced packaging. SkyWater serves the growing markets of aerospace & defense, automotive, biomedical, industrial and quantum computing. For more information, visit: www.skywatertechnology.com.
VP Quality & Reliability, Advanced Packaging Technology & Service
Day 1 / 09:00 - 09:30
With the development of 3DIC and associated packaging technologies, semiconductor industry has extended performance and density optimization to system level, complementary to traditional chip scaling. Amid broader adoption of TSMC’s advanced 2.5D/ 3D packaging solutions along with growing chiplet complexity and form factor, the interaction between Si, packaging and components become increasingly crucial and requires continue innovations on design, process development and manufacturing.
With 3DFabric Alliance, we are extending OIP collaboration to packaging/ testing and working with industry partners on substrate and memory technology development for integrated system-level design solution to customers, together with the ecosystem of OSATs, material and equipment suppliers. In parallel, we also establish the worldwide first fully automated factory to offer best flexibility for our customers to optimize their packaging solution with better cycle time and quality control.
Dr. Jun He is Vice President of Quality & Reliability as well as Advanced Packaging Technology & Service at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). His responsibility spans across TSMC foundry eco-system and the Company’s backend business and operations management. Within the Q&R scope, his function covers incoming materials qualification, reliability and certification of new process technology & design IP, manufacturing quality as well as enabling customers for their product qualification and ramp. Besides overseeing all TSMC advanced packaging and testing manufacturing, his backend team is also accountable for key building blocks including bump/passivation/RDL process innovations and test technology development. Seamless collaboration and joint development with external partners across material, OSAT and substrate supply chain is one of his focus areas to enable customers’ product innovations at system level.
Prior to joining TSMC, Dr. He was a senior director at Intel Corporation, leading overall quality and reliability of process technology development and manufacturing. His scope included research & development of Si, advanced packaging and test along with Intel worldwide manufacturing operations.
Dr. He holds over 40 patents globally and published 50 papers in international conferences and peer-reviewed technical journals. He received his B.S. degree in Physics and Ph.D. in Materials Science from University of California, Santa Barbara.
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
TSMC deployed 288 distinct process technologies, and manufactured 11,878 products for 522 customers in 2024 by providing the broadest range of advanced, specialty and advanced packaging technology services. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.
Chief AI Officer, SVP of Engineering
Day 1 / 13:25 - 13:55
This keynote will explore the impact of deep learning including large language models on the semiconductor test. We will highlight the opportunities these models present for real-time data processing and discovery of insights, with specific applications in computer vision and natural language processing. However, the use of these models also introduces new security risks, particularly regarding the use of cloud infrastructure for collection of data, training and inference. By examining past attacks on networks, we will discuss the potential for malicious actors to steal data or intellectual property from companies. Attendees will gain an understanding of the opportunities and challenges in AI and security for the coming years and the importance of considering security measures in the development and deployment of these advanced solutions.
Claudionor N. Coelho is the Chief Artificial Intelligence Officer and SVP of Engineering at Advantest, being responsible for AI strategy for Advantest and leading engineering for ACS.
Previously, he was the VP/Fellow for AI – Head of AI Labs at Palo Alto Networks, where he led AI and Neurosymbolic innovation for AIOps products at Palo Alto Networks. He also led the creation of next-generation time series analysis tools at scale (MLOps on GCP) integrated with knowledge graphs and formal technology.
He worked on Machine Learning/Deep Learning at Google. He is the creator of QKeras, a Deep Learning package for quantization on top of Keras with support for automatic quantization, being used by CERN (which made it to the cover page of Nature Machine Intelligence in August 2021). He was the VP of Software Engineering, Machine Learning, and Deep Learning at NVXL Technology. He did seminal work on AI at Synopsys Inc, and he opened the site for Cadence Design Systems in Brazil, being the GM for the site, following the acquisition of Jasper Design Automation, where he was the Worldwide SVP of R&D. Under his leadership, Jasper was awarded one of the most innovative companies in the US in 2013, according to Red Herring.
He created the initial strategy for Kunumi (when he was an angel investor), and he is an investor and is on the TAB of ConDati. He has more than 100 papers, patents, academic, and industry awards. He is currently an Invited Professor for Deep Learning at Santa Clara University, and previously, he was an Associate Professor of Computer Science at UFMG, Brazil, when he took the ACM Programming Contest to the Southern Hemisphere. He has a Ph.D. in EE/CS from Stanford University, an MBA from IBMEC Business School, and an MSCS and BSEE (summa cum laude) from UFMG, Brazil.
Advantest (TSE: 6857) is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors for applications including 5G communications, the Internet of Things (IoT), autonomous vehicles, artificial intelligence (AI), machine learning, smart medical devices and more. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also conducts R&D to address emerging testing challenges and applications, produces multi-vision metrology scanning electron microscopes essential to photomask manufacturing, and offers groundbreaking 3D imaging and analysis tools. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and an international commitment to sustainable practices and social responsibility. More information is available at www.advantest.com.
Advantest’s core product line, semiconductor test equipment, is used by IC manufacturers to test their semiconductors with high accuracy and efficiency, ensuring that they operate properly and meet performance and reliability requirements. The company uniquely provides one-stop shopping for the test cell, which includes test systems, test handlers, and device interfaces which are essential to semiconductor package test. In addition, Advantest Test Solutions offers a series of SLT and Burn-In solutions that can span from high mix/low volume applications to those that have the volume to require fully automated solutions, while Advantest’s SSD Test Systems allow customers to grow their product portfolios while remaining adaptable to the changing needs of the SSD market. The newly introduced Advantest Cloud Solutions™ (ACS) is an ecosystem of cloud-based products and technologies based on a single scalable data platform that allows customers to accomplish intelligent data-driven workflows. Advantest supports globally distributed semiconductor supply chains from locations around the world.
Co-Founder & CTO
Day 2 / 13:45 - 14:15
Ryan Rusnak is a software engineer with a master’s degree in Human Computer Interaction from Carnegie Mellon University. Before co-founding Airspace, Ryan wrote software solutions for the Federal Government. Throughout his career, he has built robots and other projects that have been featured in Popular Science, the Discovery Channel, NBC, BBC, WIRED, Gizmodo, and other media outlets. Ryan teamed up with Nick in 2016 to create Airspace in order to solve the two main inefficiencies in critical logistics: transparency and speed.
Whether your production line is facing a shutdown, or your high-value equipment is waiting for a new component, you can’t afford a shipping delay. From life-saving organs to essential machinery components, Airspace is trusted by the world’s largest companies and most critical organizations to move their top time-sensitive shipments on time, every time.
Airspace’s proprietary AI-powered platform is the most advanced of its kind- awarded and protected by multiple patents, it provides speed, reliability, routing, tracking visibility and transparency unrivaled in time-critical logistics. It powers a 24/7/365 pro-active expert support team that understands the needs of vertical specific shipments such as those in the semiconductor business.
With offices in the United States in Southern California, Dallas, and in Europe in Amsterdam and new offices in Frankfurt, Stockholm, and Paris, London, Porto, Airspace is rapidly scaling into new markets and industries while continuing to innovate and maximize value for its customers. Backed by leading investors including Telstra, HarbourVest, Prologis, Qualcomm, Defy, and others, Airspace has raised $70M to date.
Whether your production line is facing a shutdown, or your high-value equipment is waiting for a new component, you can’t afford a shipping delay.
Airspace’s proprietary AI-powered platform is the most advanced of its kind- awarded and protected by multiple patents, it provides speed, reliability, routing and transparency unrivaled in time-critical logistics. It powers a 24/7/365 pro-active expert team that understands the specific needs of shipments such as those in the semiconductor business.
From NFO, to OBC, dedicated drives, charters and more, the Airspace technology will calculate the best routing for you, taking your specific requirements into consideration as well as automating the process to save your team valuable time.
Your supply chain is complicated — we make it easy for you.
Senior Fellow Advanced Packaging
Day 1 / 12:45 - 13:25
Deepak Kulkarni is a Fellow, Advanced Packaging at AMD. Deepak has over 15 years of experience in packaging technology development. Over the years, he has held several leadership positions driving substrate technology development and yield improvement. Prior to joining AMD, Deepak was Senior Director of packaging yield at Intel Corporation. He holds 17 patents and nineteen publications on various aspects of packaging such as 2.5D/3D architectures, DFM/DFY and AI techniques applied to yield management. His contributions to the semiconductor industry have been recognized by an Intel Achievement Award, Next 5% award (AMD) and best paper award (ITHERM). Deepak holds a PhD from the University of Illinois Urbana-Champaign with a major in mechanical engineering and a minor in computational science.
For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.
Managing Director
Day 2 / 15:40 - 16:10
José J. García, Ph.D. is the Managing Director of Wafer Fab Sustainability and Autonomous Enterprise at Analog Devices. He received a B.S. Chemical Engineeering degree from the California Institute of Technology (Caltech) and a Ph.D. Chemical Engineering degree from Cornell University. Upon completion of his Ph.D., José joined Intel’s Portland Technology Development organization to develop Lithographic processes for 6 technologies down to the 32nm node. In 2009, José joined Maxim Integrated to help transform its Beaverton semiconductor facility (fab) to best-in-class safety, quality, output and cost levels thru various process, equipment and procurement directorship positions. Upon Analog Devices’ acquisition of Maxim Integrated in 2021, José secured critical items such as Silicon and Capital Equipment to enable a doubling of output in ADI’s internal fab network with minimal clean room expansion. José is now leading the Manufacturing 4.0 and Net Zero Manufacturing Enablement of ADI’s internal factory network.
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With reported revenues of more than $12 billion in FY22 and more than 24,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible. Learn more at www.analog.com and on LinkedIn and Twitter.
VP & GM Core Packaging Products
Day 1 / 11:00 - 11:10
Heterogeneous design and integration has been referred to as the fourth stage in the evolution of Moore’s Law, as it enables us to integrate sets of chiplets into high performance computing packages with simultaneous improvements in power, performance, and area-cost. The need for high bandwidth and power-efficient interconnects between chiplets is driving new process technologies and automation technologies that address the higher feature densities and higher sensitivity to defects.
Large form factor panel-level processing enables higher manufacturing productivity at low cost but introduces several manufacturing challenges. The higher density of interconnections requires fine line capability that presents a challenge to traditional process equipment. Warping of the large and flexible substrates presents challenges both for handling the panels as well as the formation of reliable interconnects. The complexity of assembling multi-chiplet packages requires new factory automation solutions that can maximize product quality and factory utilization.
High resolution patterning can be achieved with materials and technologies from traditional front end processing, including PVD, Dry Etch, CVD and ALD. With its broad portfolio of semiconductor and display fabrication technologies and products, Applied Materials is addressing the challenge of delivering Front End manufacturing capability at Back End cost requirements. This presentation will highlight Applied innovations that enable panel level packaging and the factory of the future.
Len Tedeschi is vice president and general manager, Core Packaging Products at Applied Materials. Len is directly responsible for the Metals Packaging Products (MPP), Packaging Plating & Cleans (PPC), Tango & Plasma Dicing product groups. His focus is ensuring customers are successful with their current products, while simultaneously solving customer’s future high value problems.
Len has worked at Applied for >20 years and has over 27 years of semiconductor experience in roles ranging from product development & support, productivity, technical strategy, marketing, and general management. Len has worked with a variety of products and technologies including etch, deposition, lithography, metrology, and inspection.
Prior to joining Packaging, Len spent 14 years in Applied’s Etch Business Unit in a wide variety of customer focused positions. Len has >10 patents granted, mainly as the lead author.
Len began his career in 1995 as a lithography equipment engineer at IDT in Santa Clara, California.
He earned a bachelor of science degree in industrial technology from San Jose State University in 1995, where he served as captain of the university’s judo team, winning two collegiate national titles, and competing in the 1996 Olympic Judo Trials.
We are the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations Make Possible® a Better Future.
Associate Professor and Director of Faculty Entrepreneurship
Day 1 / 08:10 - 08:30
Greater Phoenix is home to an ever-expanding ecosystem of semiconductor manufacturing and its supply chain. Long-term strategic planning of resources at the state and regional level have supported this growth, ensuring that adequate water and nation-leading grid reliability meet the needs of industry. Paired with a robust workforce and an educational system anchored by Arizona State University and the Maricopa County Community College District, the region has the requisite labor force to meet the needs of key industry sectors. Greater Phoenix is a top global destination for businesses and uniquely positioned to seize the momentum of technological innovation and advanced industry to support future development.
Zachary Holman is an Associate Professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University, as well as the Director of Faculty Entrepreneurship within the Fulton Schools of Engineering. He received his Ph.D. in Mechanical Engineering from the University of Minnesota for his work on plasma-synthesized silicon and germanium nanocrystals, after which he spent two years as a postdoctoral researcher developing high-efficiency silicon solar cells at Ecole Polytechnique Fédérale de Lausanne in Switzerland. His research group at ASU focuses on new materials, processes, and device designs for high-efficiency silicon solar cells and silicon-based tandem solar cells. He has been named a Moore Inventor Fellow, Trustees of ASU Professor, Fulton Entrepreneurial Professor, and Joseph C. Palais Distinguished Faculty Scholar. He is the co-founder of two solar start-up companies (Sunflex Solar and Beyond Silicon) and an advanced materials start-up company (Swift Coat).
With 110,000+ undergraduate students, 30,000+ graduate and professional students, and 5,000+ faculty, Arizona State University (ASU) exemplifies a new prototype for the American public research university. At ASU, our culture of innovation and inclusion draws pioneering researchers to our faculty and attracts highly qualified students from all 50 states and more than 130 nations. ASU is expanding academic and entrepreneurial opportunities for every type of learner at all stages of life. Creating a resilient microelectronics innovation ecosystem is critical to America’s security and economic competitiveness. Arizona State University is responding to this need by working with industry and government partners to reestablish America’s capacity for domestic microelectronics and semiconductor manufacturing and innovation. ASU offers traditional degree programs and rapid, low-cost options for upskilling and re-skilling of the existing semiconductor workforce, as well as workers from outside the industry.
ASU is building the semiconductor talent pipeline and mobilizing the expertise and capabilities of the Fulton Schools of Engineering to drive research, development and innovation. The Fulton Schools of Engineering at Arizona State University is the largest and most comprehensive engineering school in the nation, offering 25 undergraduate degree programs, and 48 graduate degree programs. With over 30,000 students within the Fulton Schools of Engineering, 7000+ students studying microelectronics-related fields, and 150+ faculty engaged in microelectronics research and teaching. We offer extensive research facilities including our research in semiconductor manufacturing and advanced semiconductor packaging which is supported by our extensive lads which includes MacroTechnology Works with 250,000 total sq ft capacity, 43,000 sq ft clean rooms, and 23,00 sq ft wet/dry labs. We also offer graduate programs in semiconductor manufacturing, packaging, and assembly as well as certificate programs to support workforce development.
AVP Panel Products
Day 1 / 16:05 - 16:15
Applications for Artificial Intelligence (AI) have grown substantially over the last few years in the legal, medical, and automotive industries. These business sectors are regulated more heavily than semiconductor manufacturing equipment is, but use of AI in the semiconductor industry is lagging. The costs and benefits of AI are relatively easy to project, so it follows that AI has been studied and found that large-scale adoption provides an insufficient return on investment. A cost model will be proposed showing likely AI growth areas such as automated maintenance tasks and performance benchmarking, and a few that may remain out of reach.
Jon Hander is Assistant Vice President of Panel Products for ASM NEXX. He has worked at NEXX since 2011 and in the semiconductor industry since 1996. In his career, Jon has served in manufacturing, service, process, sales, development & product management roles. Jon has a BS in Engineering Technology from Texas A&M University.
ASMPT, founded in 1975, is headquartered in Singapore and is listed in Hong Kong Stock Exchange since 1989.
ASMPT is the only company in the world that offers high-quality equipment for all major steps in the electronics manufacturing process – from carrier for chip interconnection to chip assembly and packaging to SMT. No other supplier offers a comparable range and depth of process expertise.
Semiconductor Solutions Segment Business of ASMPT offers a diverse product range from bonding to molding and trim & form to the integration of these activities into complete in-line systems for the microelectronics, semiconductor, camera modules, advanced packaging, photonics, and optoelectronics industries.
The group has successfully established itself as the leading player in the back-end assembly and packaging market with its innovative solutions and constant focus on customer value creation.
SVP Strategic Business Engagements and Supplier Management
Day 2 / 13:45 - 14:15
Rebeca Obregon-Jimenez is Avnet’s senior vice president of strategic business engagements and supplier management. She creates strong, long-lasting relationships for the Avnet Integrated, Avnet United and Avnet Velocity business units. She also oversees supplier management for the Interconnect, Passive & Electromechanical (IP&E) business and drives strategy, mergers and acquisitions across the organization.
With more than 30 years of experience in the semiconductor industry, Obregon-Jimenez has built and grown teams and businesses from inception to profitable worldwide market leaders. Before joining Avnet, she served as a corporate vice president at Amkor Technology. She also held a variety of strategy, management, operations and engineering roles at IDT and Motorola.
Obregon-Jimenez earned a bachelor’s degree in electrical engineering from Arizona State University and a master’s degree in electrical engineering from the National Technological University. She serves on the board of directors of FormFactor, Inc., a provider of essential test and measurement technology for integrated circuits.
Avnet (Nasdaq: AVT) is a leading global technology distributor and solutions provider that has served customers’ evolving needs for more than a century. Avnet’s position at the center of the technology value chain enables it to accelerate the design and supply stages of product development so customers can realize revenue faster. Headquartered in Phoenix, Arizona, Avnet serves more than 1 million customers in more than 140 countries and partners with global suppliers from almost every technology segment. At the close of FY22, Avnet generated $24.3 billion in sales and operated 12 major distribution centers, 11 technology campuses, six programming centers, and 250+ facilities in 45+ countries. Learn more about Avnet at www.avnet.com
(480) 643-2000
Corporate.Communications@Avnet.com
CEO
Day 2 / 11:40 - 12:05
As AI model sizes continue to grow, models will have 100 trillion or more connections, exceeding the technical capabilities of existing AI platforms. New optical interconnect solutions that enable novel system architectures are needed to address the scale, performance and power demands of the next generation of AI. The latest advancements in optical I/O, a new generation of chiplet and multi-wavelength laser solutions, provide dramatically increased bandwidth, at lower latency, over longer distances and at a fraction of the power of existing electrical I/O solutions. In this talk, we present the convergence of trends in compute applications, new optical and advanced packaging technologies, and a scalable supply chain ecosystem, leading to opportunities to build paradigm shifting system architectures addressing AI/ML and cloud computing applications.
Mark is Chief Executive Officer and Co-Founder of Ayar Labs. His prior roles at Ayar Labs include Chief Technology Officer and Senior Vice President of Engineering. He is recognized as a pioneer in photonics technologies and, prior to founding the company, led the team that designed the optics in the world’s first processor to communicate using light. He and his co-founders invented breakthrough technology at MIT and UC Berkeley from 2010-2015 which led to the formation of Ayar Labs. He holds a PhD from University of Colorado.
Ayar Labs is disrupting the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by driving a 1000x improvement in interconnect bandwidth density at 10x lower power. Ayar Labs’ patented approach uses industry standard cost-effective silicon processing techniques to develop high speed, high density, low power optical based interconnect “chiplets” and lasers to replace traditional electrical based I/O. The company was founded in 2015 and is funded by a number of domestic and international venture capital firms as well as strategic investors. For more information, visit www.ayarlabs.com.
Address: 695 River Oaks Parkway, San Jose, CA 95134
Phone: 650-963-7200
Email: info@ayarlabs.com
Director Global Key Account Management
Day 2 / 14:35 - 14:40
The global demand for high-end computing power driven by smartphones, IoT applications, High-performance computing, and new mobility applications is constantly rising while facing miniaturization demands. The semiconductor industry is all about identifying and solving these challenges and thereby, yield and process control is core for foundries and its importance increased even more through the introduction of advanced packaging. In today’s environment, two things can be observed. One, prototyping and verification costs exponentially increase while node sizes decrease. Two, a change from typical inspection methods like optical or FIB-SEM to advanced non-destructive inspection techniques like X-ray inspection. Ultimately advanced packaging companies seek non-destructive automated inspection tools which are fast enough to provide value within their production processes, increase yield and reduce waste at an early stage. This presentation will give an overview on how X-Ray and CT inspection can provide value-added data and information for exactly that.
Enrico Haertel is the Director of Global Key Account Management at Comet YXLON. Focusing on x-ray inspection tasks, he is working with customers on solutions to reduce time-to-market and increase yield.
He began his career in the FinTech industry, introducing, among others, contactless payment technology into the European market. Then, switching gears in 2011, he joined the field of inspection solutions for the Semiconductor and SMT world, gaining expertise in testing solutions like wafer probe cards and optical and x-ray inspection.
Building on decades of experience and an unfailing passion for technology, Comet Yxlon is a globally leading company for industrial X-ray and CT system solutions. Manufacturers in the aerospace, automotive, electronics, and semiconductor industries rely on Comet Yxlon to maximize their product quality and the efficiency of their production. From cutting-edge inspection systems to the award-winning user interface Geminy – at Comet Yxlon, we support our customers with innovative products and services that help them shape future markets.
From single die traditional packages to wafers and advanced packaging devices – we supply manufacturers with X-ray inspection systems that meet the high standards of semiconductor quality control. Speed, resolution, 2D or 3D – depending on the application, manufacturers have different priorities for the inspection of semiconductor products. We offer a variety micro- and nano-focus inspection systems providing digital radioscopy, computed laminography, and computed tomography for optimum test results for increased yield.
Director Business Development
Day 1 / 16:45 - 17:30
Robin Davis is the Director of Business Development at Deca Technologies, an industry leading semiconductor interconnect solutions company. She focuses on identifying new opportunities for the powerful miniaturization and performance benefits of Deca’s M-Series and Adaptive Patterning Technologies. Additionally, she works closely with both internal and customer R&D teams to drive next generation products and technological advances. She is both a contributor and lead inventor on many of Deca’s patents. Previously, Robin fulfilled the role of Senior Solutions Architect at Deca, where she collaborated with customers, suppliers, and Deca’s engineering team to advance package design and interconnect solutions. Robin started her career as a semiconductor packaging engineer at Lattice Semiconductor before transitioning to Advanced Packaging Tools Technical Marketing Engineer at Mentor Graphics (now Siemens EDA). Robin graduated with her BSEE from Portland State University. She is a member of the Tau Beta Pi and IEEE Eta Kappa Nu Honor Societies. Robin also serves as chair of the Diversity, Equity and Inclusivity committee for the International Microelectronics and Packaging Society (IMAPS).
Deca is the semiconductor industry’s leading independent development, implementation and licensing provider of advanced packaging technology offering M-Series, the #1 volume fan-out technology and Adaptive Patterning, empowering designers with breakthrough ultra-high-density interconnect capability.
Managing Director
Day 2 / 15:40 - 16:10
Dr. Bobby Mitra is currently Managing Director at Deloitte Consulting, and Consulting leader for Global Semiconductor & Hi-Tech Manufacturing, Supply-Chain and Engineering Practice. Prior to his current role, he was at Texas Instruments as the Worldwide Director of Smart Manufacturing across TI’s 300mm & 200mm wafer fabs and assembly/test sites. In this role, he led several activities around manufacturing automation, multi-year factory-of-the-future roadmap, quality/yield improvement, asset utilization, cycle time optimization, manufacturing productivity etc.
Prior to that, he led TI’s worldwide Industrial Systems across 14 sectors, including factory automation, motor control, smart grid, building automation, test & measurement, medical, appliances etc. He had also led all of Texas Instruments’ operations in India as President & Managing Director, leading all R&D, Sales, Marketing, Research etc.
Dr. Mitra was elected IEEE Fellow, and is Chairman of SEMI Global & Americas Smart Manufacturing. He holds a B.Tech degree in Electronics & Electrical Communications Engineering, and Ph.D in Computer Science & Engineering, both from Indian Institute of Technology (IIT), and an Executive MBA from University of Texas at Austin.
Deloitte provides industry-leading audit, consulting, tax and advisory services to many of the world’s most admired brands, including nearly 90 percent of the Fortune 500® and more than 7,000 private companies. Our people come together for the greater good and work across the industry sectors that drive and shape today’s marketplace delivering measurable and lasting results that help reinforce public trust in our capital markets, inspire clients to see challenges as opportunities to transform and thrive, and help lead the way toward a stronger economy and a healthier society. Deloitte is proud to be part of the largest global professional services network serving our clients in the markets that are most important to them. Building on more than 175 years of service, our network of member firms spans more than 150 countries and territories. Learn how Deloitte’s more than 330,000 people worldwide connect for impact at www.deloitte.com.
Business & Political Journalist
Day 2 / 16:10 - 16:40
General Manager STC Americas
Day 1 / 16:45 - 17:30
Najwa Khazal has more than 20 years’ experience in the delivery of business transformation programs across a range of industries, including energy, aerospace and automotive, in America, China, EMEA, India and Mexico. Her successful track record in driving value creation programs spans supply chain management, product lifecycle management, process integration, digital transformation and organizational change.
Najwa joined Edwards as General Manager for the Service Technology Centres (STC) Americas organisation in April 2021, responsible for defining, implementing and facilitating the strategic initiatives needed to support the future growth of Edwards and its customers in the semiconductor industry. Najwa has responsibility for the operational performance and management of remanufacturing facilities located in Glenwillow and Hillsboro in the US, Nogales in Mexico, and Sao Paulo in Brazil.
Prior to joining Edwards, Najwa was General Manager for Collins Aerospace.
Najwa has a broad education, achieving a distinction from the Harvard Business Analytics Program, a Master of Business Administration and a Bachelor of Science in Mechanical Engineering Technology.
Najwa is a passionate advocate for STEM (science, technology, engineering, maths) education, and has spent more than a decade facilitating international business and organizational development classes for undergraduate and master level students.
Najwa is a US citizen and is based in Arizona.
Co-Founder & CEO
Day 2 / 12:05 - 12:30
Industry has been looking for ways to implement high-performance system in package (SiP) solutions by mixing and matching existing off-the-shelf chiplets. However, due to lack of a universal standard for chiplet interfaces, and connections, this has not yet been practical and achievable. In addition, people have often depended on complex and expensive advanced packaging structures (e.g., large silicon interposers) to build their large SiPs. A new chiplet PHY technology that provides high performance (high bandwidth/power efficiency and low latency) over standard organic package substrates is presented. In addition, an innovative interfacing product that converts any chiplet interface to the new PHY enables practical mix and match of chiplets with different die-to-die interfaces and in different processes. The combined solution not only enables mixing and matching of chiplets, but also provides such option over standard packaging, reducing the total cost of the solution.
Ramin Farjadrad, president and co-founder of Eliyan Corporation. Ramin, a previous speaker at ISES, is the founding CEO of Eliyan, a start-up focused on addressing interconnect challenges in multi-die architectures. He is the inventor of over 140 granted and pending patents in communications and networking and has a successful track record of creating differentiating connectivity technologies adopted by the industry as international standards (including two Ethernet standards at IEEE, and the BoW chiplet connectivity adopted by OCP.) Prior to Eliyan, Ramin co-founded Velio Communications, which led to a Rambus/LSI Logic acquisition, and Aquantia, which IPO’d and was acquired by Marvell Technologies. Ramin has a Ph.D. EE from Stanford.
Eliyan Corporation, credited for the invention of the semiconductor industry’s highest-performance and most efficient interconnect on multi-die architectures, is leading the chiplet revolution by enabling the creation of ultimate chiplet systems. Its technology addresses the fundamental challenges with semiconductor scaling to meet the needs of high-performance computing applications, from desktop to datacenter. It has developed a breakthrough method to enable the industry’s highest performing interconnect for homogenous and heterogenous multi-die architectures, enabling increased sustainability through reduction in costs, manufacturing waste and power consumption. The company’s Bunch of Wires (BoW) PHY, invented by founder Ramin Farjadrad and proven to increase performance by 2x and reduce power in half, provides a more efficient approach to developing chiplet-based architectures. The company has received initial funding from strategic investors, including Intel Capital and Micron Ventures, and venture capital firms Tracker Capital Management and Celesta Capital. It is based in Santa Clara, California.
Managing Director
Day 2 / 10:30 - 11:00
The presentation will apply a financial lens to the current state of the semiconductor industry. The discussion will evaluate key industry and economic trends, and assess factors that will shape the industry in years to come, including government support and regulations. It will also provide perspectives on sector valuations, strategic transaction activity and potential future consolidation.
Mr. Chakrabarti is a Managing Director in the firm’s corporate advisory business focusing on the Technology sector.
Mr. Chakrabarti has advised leading technology firms and financial sponsors on M&A and capital markets transactions including Mobileye on its $961M IPO, NxEdge on its $850M sale to Enpro, AvePoint on combination with Apex Technology and subsequent public listing, Conservice on sale of TA Associates’ equity stake to Advent International, Conservice on its sale of majority stake to TA Associates, Enersys on the $750M acquisition of Alpha Technologies Group of Companies, Akamai on its defense and cooperation agreement with Elliott Management, Cobham on its $455M divestiture of AvComm and Wireless businesses to Viavi, Samsung on the $9B acquisition of Harman, Qualcomm on the $49B announced (and subsequently cancelled) acquisition of NXP Semiconductors, Sonus on a merger of equals with Genband, Siris Capital’s $943M acquisition of PGi, Cbeyond on its $323M sale to Birch, and financing of TPG led group’s acquisition of Cirque du Soleil.
Prior to Evercore, Mr. Chakrabarti was an Associate Director at UBS in their Technology, Media and Telecommunications Group in New York. He holds a MBA from Cornell University’s SC Johnson Graduate School of Management and a BA in Economics from University of Delhi, India.
Evercore Inc., formerly known as Evercore Partners, is a global independent investment banking advisory firm founded in 1995 by Roger Altman, David Offensend, and Austin Beutner. Evercore’s Investment Banking business advises its clients on mergers and acquisitions, divestitures, restructurings, financings, public offerings, private placements and other strategic transactions and also provides institutional investors with macro and fundamental equity research, sales and trading execution. Evercore’s Investment Management business comprises wealth management, institutional asset management and private equity investing. Evercore serves clients from 28 offices in North America, Europe, South America and Asia. Since 1995, the firm has advised on more than $3 trillion of merger, acquisition, recapitalization, and restructuring transactions.
Senior Managing Director
Day 2 / 10:30 - 11:00
The presentation will apply a financial lens to the current state of the semiconductor industry. The discussion will evaluate key industry and economic trends, and assess factors that will shape the industry in years to come, including government support and regulations. It will also provide perspectives on sector valuations, strategic transaction activity and potential future consolidation.
Tom Stokes is a Senior Managing Director of Evercore’s corporate advisory business and co-leads the Technology Banking Group in New York.
Tom is focused on advising clients across the technology sector.
Prior to joining Evercore in 2015, Tom was a Managing Director in the Investment Banking Division at Goldman, Sachs & Co., where he served as global head of Electronics and Industrial Technology Investment Banking. With over 25 years of relevant experience and over 13 years at Goldman Sachs, Tom has extensive experience advising companies across the technology industry. In particular, he has advised on a number of the most notable recent transactions across the semiconductor, electronics and industrial tech subsectors. Clients represented by Tom include Advanced Energy, Aeroflex, Anaren, Amphenol, AZ Electronic Materials, Azenta, Belden, Brooks, CDW, Cobham, Corning, Dover, Dupont, Edwards, Entegris, Fortive, Freescale, IBM, Lam Research, Lexmark, Macom, Molex, Keysight, Koch Industries, TE Connectivity, Samsung, Sensata, Solectron, Tokyo Electron, Universal Display and Viasystems, among others.
Tom received his BA, MA and MEng degrees (First Class) in Engineering from Cambridge University and received his MBA degree from Kellogg School of Management.
Evercore Inc., formerly known as Evercore Partners, is a global independent investment banking advisory firm founded in 1995 by Roger Altman, David Offensend, and Austin Beutner. Evercore’s Investment Banking business advises its clients on mergers and acquisitions, divestitures, restructurings, financings, public offerings, private placements and other strategic transactions and also provides institutional investors with macro and fundamental equity research, sales and trading execution. Evercore’s Investment Management business comprises wealth management, institutional asset management and private equity investing. Evercore serves clients from 28 offices in North America, Europe, South America and Asia. Since 1995, the firm has advised on more than $3 trillion of merger, acquisition, recapitalization, and restructuring transactions.
Chief Marketing Officer and Senior Vice President, Mergers and Acquisitions
Day 1 / 16:45 - 17:30
Amy Leong has been with FormFactor since October 2012. Prior to this, Amy was the VP of Marketing at MicroProbe from April 2010 through the October 2012 closing of FormFactor’s acquisition of MicroProbe. Before joining MicroProbe, Ms. Leong worked at Gartner, Inc. as a Research Director from 2008 to 2010 and covered the ASSP system-on-chip and microcontroller markets. From 2003 to 2008, Ms. Leong worked at FormFactor where she served as Senior Director of Corporate Strategic Marketing and Director of DRAM Product Marketing. Prior to FormFactor, Ms. Leong worked in a variety of semiconductor process engineering and product marketing roles at KLA-Tencor and IBM.
Ms. Leong holds an M.S. in Material Science and Engineering from Stanford University and a B.S. in Chemical Engineering from the University of California, Berkeley.
FormFactor is a leading provider of essential test and measurement technologies along the full IC life cycle – from characterization, modeling, reliability, and design debug, to qualification and production test. Semiconductor companies rely upon FormFactor’s products and services to accelerate profitability.
FormFactor’s leading-edge probe stations, probes, probe cards, advanced thermal subsystems, quantum cryogenic systems and integrated systems deliver precision accuracy and superior performance both in the lab and during production manufacturing.
Visit www.formfactor.com or follow us on LinkedIn.
Founding Director and Emeritus Professor
Day 2 / 16:10 - 16:40
Prof. Rao Tummala is a Distinguished and Endowed Chair Professor and Director Emeritus at Georgia Tech in USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech in 1993, he was an IBM Fellow and Director of Advanced Packaging Lab(APTL), pioneering such major technologies as the industry’s first plasma display in the 1970’s and the first and next two generations of 100-chip MCM package integration, now called chiplet MCMs, in 1980″s for servers, mainframes, and supercomputers. He is the father of System-on-Package(SOP) concept Vs. System-on-chip (SOC.) As an educator, Prof. Tummala was instrumental in setting up the largest and most comprehensive Academic Center funded by NSF as the 1st and only NSF Engineering Research Center in Electronic Systems Packaging at Georgia Tech. Such a Center, under his leadership, pioneered an integrated approach to research, education, and global industry collaborations. It involved about 30 academic and full-time research faculty,200 Ph.D. and MS students and 50-70 industry and academic collaborators from US, Europe, Japan, Korea, India and Taiwan.. It educated thousands of engineers in packaging in classrooms and labs.,and produced more than 1000 engineers with Ph.D., MS and BS degrees,. He has published about 800 technical papers and invented technologies that resulted in over 110 patents and inventions. He has been pioneering glass-based electronics as the most leading-edge packaging technology beyond Silicon interposers that is targeted to go into production In 2023.
He wrote the first modern handbook in packaging, Microelectronics Packaging Handbook( McGraw-Hill,1988); then 1st undergrad textbook, Fundamentals of Microsystem Packaging(2001); the 1st book introducing the concept of SOP, Introduction to System-on-Package( 2006) and the 2nd edition of Fundamentals of Device and Systems Packaging (2020). He received more than 50 Industry, Academic and Professional Society awards, including. 12Invention and 4 Corporate Awards from IBM, IEEE Award David Sarnoff Award for Industry’s First MCM in 1991 ,ASM-International: Engineering Materials Achievement Award for LTCC in 1992,IEEE CPMT: Sustained Technical Achievement Award in 1992,European Electronic Materials Award from DVM in 1995,,International Microelectronic & Packaging Society’s (IMAPS): Dan Hughes Award in 1997,American Ceramic Society’s John Jeppson Award in 1998,IMAPS’: John A. Wagnon’s Award in 1991,IMAPS: John A. Wagnon’s Award , Named by US News and World Report as one of the 50 Stars in US for US competitiveness in 1999,Total excellence in Manufacturing Award from ASE in 2000,Educator of the Year for Excellence in Teaching, Research, and Innovation in Electronics from the India-America Cultural Association in 2002 andTechno-visionary Award from Semiconductor Industry Association of India in 20110. In addition, he is a distinguished Alumni of
Indian Institute of Science, Bangalore in 2000 , India,;University of. Illinois in 1988 and Distinguished Faculty of Georgia Tech in 2002
He is a member of NAE in USA. And NAE in India and IEEE, IMAPS and Am Ceramic Society Fellow, and President of IEEE CPMT and IMAPS Societies. He has been a consultant and advisor to many of Fortune 500 semiconductor and systems companies
IEEE recently named him as the father of modern Packaging and created a technical field award in his name—IEEE Rao Tummala Electrronics Packaging Award’
Executive Vice President
Day 1 / 18:00 - 19:00
Tal Levin serves as the Executive Vice President at Green Technology Investments LLC (GTi), headquartered in Scottsdale, Arizona, USA. GTI specializes in AMAT Metrology, encompassing a range of cutting-edge technologies such as SEMVision, Defect Review “DR-SEM,” VeritySEM, Critical Dimension SEM “CD-SEM”, and Compass & ComPLUS, Darkfield Inspection systems.
Having co-founded GTI in 2012, Tal has played a pivotal role in driving global sales initiatives until recently, when he shifted his focus to overseeing the technology roadmap and strategic procurement activities for both domestic and international clients.
In line with GTI’s growth strategy in 2023, the company underwent a transformation, establishing two distinct divisions: Metrex and RT-Ex. Additionally, GTI secured exclusive representation rights for the etrology™ software measurement solutions.
With over 32 years of experience in the semiconductor industry, Tal Levin is a seasoned executive with a profound understanding of semiconductor processes. His expertise extends to establishing and managing global service and sales networks, particularly in key regions such as China, Taiwan, and Southeast Asia.
Throughout his extensive career, Tal has held significant positions at notable companies including H.T.M., Norcimbus Inc., OEM Group, and GTI, where he and the team have developed several patent applications aimed at process enhancement and measurement refinement.
Tal Levin exemplifies excellence in management, strategic planning, and international business development within the semiconductor industry, serving as a benchmark for leadership and innovation.
Green Technology Investments LLC (GTi), headquartered in Scottsdale, Arizona, is a pioneering force in the semiconductor industry. With a focus on innovative remanufacturing and software solutions, GTi aims to revolutionize how businesses access advanced technology. Since its inception, in 2012, GTi has been committed to providing high-quality equipment and expert services to its global clientele. With offices strategically located in North America, Europe, and Asia, GTi is well-positioned to meet the needs of customers worldwide. By investing in research and development, GTi continues to expand the capabilities of remanufactured equipment and software, making cutting-edge technology more accessible and affordable for businesses of all sizes. GTi’s impact on the semiconductor industry is profound, enabling businesses to compete effectively in today’s dynamic market landscape.
Green Technology Investments LLC (GTi) offers a comprehensive range of products and services tailored to the semiconductor industry’s evolving needs. Specializing in remanufacturing and software solutions, GTi provides access to advanced technology at a more affordable price point. Their product lineup includes remanufactured semiconductor equipment such as CD-SEM, DR-SEM metrology systems, and MASK systems, ensuring high-quality performance and significant cost savings compared to new systems. In addition to equipment, GTi offers ready-to-ship spare parts, expert service support, and foundry capabilities to enhance customer experience and satisfaction. With a relentless focus on innovation and customer satisfaction, GTi is dedicated to empowering businesses of all sizes with the tools they need to thrive in today’s competitive global market.
Group VP, Enabling Technologies and Semiconductors
Day 1 / 15:25 - 15:55
Day 2 / 16:10 - 16:40
Mario Morales is the group vice president of IDC’s enabling technologies, semiconductor, storage, and DataSphere research.
He is responsible for in-depth analysis, evaluation of emerging markets and trends, forecasting, and research of major semiconductor industry segments such as embedded and intelligent systems, wireless, personal computing, networking and cloud infrastructure, automotive electronics, and AI semiconductors.
BACKGROUND
Mr. Morales is an accomplished program vice president, manager, and industry expert with over 25 years of experience in building a multinational top-tier consulting, sales, and research team and driving a set of established businesses. Solid experience in managing strategic partnerships and advisory services with IDC’s largest multinational clients. Strong analytical, strategic planning skills, and managing complex projects involving strong collaboration across geographies, functional groups, and business units. Proven leadership skills and instrumental at establishing research and business KPIs.
Mr. Morales is a trusted advisor to leading high tech company executives, financial investors, and bankers on market landscape and direction, product and technology positioning, competitive benchmarking, M&A, HW, and SW technology, and brand health and sustainability. Established relationships with technology suppliers including Intel, Samsung, TSMC, Qualcomm, Huawei, HP, AMD, NVIDIA, Microsoft, Facebook, TI, Micron, UMC, SoftBank, ARM, NXP, and others.
Mr. Morales is the leading advisor and expert analyst for IDC’s largest Wall Street clients including investment banking, VC’s, and mutual and hedge funds across every major financial region.
Over his career, Mr. Morales has authored and co-authored over 240 reports and studies in the area of semiconductors, mobile, PC, wireless, embedded, IoT, and IT marketplace. His team is responsible for some of the most interesting and evolving tech in our industry including coverage of microprocessors, accelerated computing, storage, memory, sensors and connectivity. His team has been responsible for initiating coverage of emerging technologies for IDC, and driving new research business practices, and creating leading industry market models in DRAM, NAND, Embedded processors and controllers, AI ML architectures, cellular baseband modems, WiFi, cellular broadband, digital consumer, foundry, EMS, and intelligent systems.
His career includes past positions with NEC Electronics and Dataquest.
EDUCATIONAL ACCOMPLISHMENTS
IDC is the premier global provider of market intelligence, advisory services, and events for the information technology, telecommunications, and consumer technology markets. IDC helps IT professionals, business executives, and the investment community make fact-based decisions on technology purchases and business strategy. More than 1,100 IDC analysts provide global, regional, and local expertise on technology and industry opportunities and trends in over 110 countries worldwide. For more than 50 years IDC has provided strategic insights to help our clients achieve their key business objectives. IDC’s Insights businesses provide industry-focused advice for IT buyers in the Financial, Government, Health, Retail, Manufacturing and Energy verticals. IDC is a subsidiary of IDG, the world’s leading technology media, research, and events company. You can learn more about IDC by visiting www.idc.com.
SVP, CMOS Technologies
Day 2 / 09:00 - 09:30
Transistor density in chips continues to follow Moore’s law, but the node to node logic performance improvements have slowed down. Memory and power walls limit compute system performance. Future compute systems will increasingly rely on new materials, new device architectures and system technology co-optimization to realize benefits beyond pure density scaling of compute, connect and store technologies. This talk will highlight technology innovations in logic, memory and 3D integration that will enable continued compute systems scaling. With the anticipated semiconductor industry growth in the next decade, we also need collective action to address the carbon footprint of semiconductor manufacturing.
Sri Samavedam is SVP of CMOS Technologies at imec since Aug 2019. His responsibilities include programs in logic, memory, photonics and 3D integration. Prior to that, he was senior director of technology development at Globalfoundries in Malta, NY, where he led qualification of 14nm FinFET technology and derivatives into volume production and early development of 7nm CMOS.
He began his research career at Motorola in Austin, TX, working on strained silicon, metal gates, high k dielectrics and fully-depleted SOI devices. He holds a Ph.D. in Materials Science and Engineering from MIT and a masters from Purdue University.
Imec is a world-leading research and innovation center in nanoelectronics and digital technologies. Imec leverages its state-of-the-art R&D infrastructure and its team of more than 5,500 employees and top researchers, for R&D in advanced semiconductor and system scaling, silicon photonics, artificial intelligence, beyond 5G communications and sensing technologies, and in application domains such as health and life sciences, mobility, industry 4.0, agrofood, smart cities, sustainable energy, education, … Imec unites world-industry leaders across the semiconductor value chain, Flanders-based and international tech, pharma, medical and ICT companies, start-ups, and academia and knowledge centers. Imec is headquartered in Leuven (Belgium), and has research sites across Belgium, in the Netherlands and the USA, and representation in 3 continents. In 2021, imec’s revenue (P&L) totaled 732 million euro.
Further information on imec can be found at www.imec-int.com.
CEO
Day 1 / 16:35 - 16:45
Shekhar Chandrashekhar has over 30 years’ experience as a leader, strategist, and innovator with a history of driving improvements that streamline operations, drive growth and increase profitability on a global scale.
Prior to joining iNEMI, Shekhar was responsible for managing the national network of Smart Manufacturing Innovation Centers (SMICs) for the Clean Energy & Smart Manufacturing Institute (CESMII). He has also worked with the American Society of Mechanical Engineers (ASME) as managing director, programs, for the association’s executive leadership team. Shekhar began his career as a member of technical staff of AT&T Bell Labs and held several management positions with Bell Labs/Lucent Technologies/Alcatel-Lucent, including senior manager for the Network Solutions Group and Bell Labs/Supply Chain Networks. He eventually became director of the company’s CTO Group, where he created the footprint for Global Engineering Centers.
He received the Advanced Technology Excellence Award from Bell Laboratories and the Outstanding Young Manufacturing Engineer Award from SME. He has published over 25 papers in international journals and conferences.
EVP & GM Technology Development
Day 1 / 16:45 - 17:30
Dr. Ann Kelleher is the executive vice president and general manager of Technology Development at Intel Corporation. Since 2020, she is responsible for the research, development and deployment of the next-generation silicon, advanced packaging, and test technologies that power Intel’s innovation. She joined Intel in 1996 as a process engineer and has worked in areas spanning from litho, thin films, yield, to managing all of Intel’s Global operations including Fab and Assembly Test factories, supply chain and construction. She did her Ph.D. in electrical engineering from University College Cork in Ireland and her post-doc at IMEC.
Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.
To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.
Intel Fellow; Director Substrate TD Module Engineering
Day 1 / 12:45 - 13:25
Rahul Manepalli is an Intel Fellow and Sr. Director of Module Engineering in the Substrate Package Technology Development Organization in Intel. Rahul and his team are responsible for developing next generation of materials, processes and equipment for Intel’s package pathfinding and development efforts. His team has been the driving force behind many of the technology innovations in Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and other substrate technologies. Rahul has also had an instrumental role in leading Intel’s assembly materials development and pathfinding efforts leading to several innovations in encapsulants, thermal interface materials and solder alloys. Rahul is the author of over 100 patent publications in semiconductor packaging, over 50 technical papers and invited talks and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.
Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.
To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.
CVP Global Supply Chain Operations
Day 2 / 13:45 - 14:15
Jackie Sturm leads operations for Intel’s multi-billion-dollar Global Supply Chain, which has been cited as a #8 or better for nine consecutive years in Gartner’s Supply Chain Top 25. Her international team supports Construction and Facilities sourcing, Indirect procurement, business continuity, supply chain systems and analytics, and Supply Chain Environmental and Social Governance program, which includes Intel’s first-mover Conflict Minerals initiative. Jackie is a committed advocate for the criticality of value-added manufacturing, engineering and trade as the economic foundations of thriving societies. Within Global Supply Chain, Jackie sponsors targeted advancement programs to address challenges faced by women and unrepresented minorities in technology.
Jackie is a board director for KM Labs and on the board of advisors for Banff International Research Station, Gartner/SCM Word, Howard University Center for Supply Chain Management, and Women’s Business Enterprise National Council (WBENC). Prior to joining supply chain, Jackie held various finance positions at Intel, including CFO for Technology and Manufacturing, as well as at Hewlett Packard, Ridge Computer, and Apple.
Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.
To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.
Co-Founder
Day 2 / 09:30 - 10:30
Workshop by International SubFAB Research Labs Initiative (ISRL)
One of the key areas poised to become a showstopper for the industry’s ability to achieve sustainability goals is commonly called SubFAB. Existing infrastructure can’t support true game changing development of environmentally friendly and affordable solutions to match the manufacturing technologies advancement cadence.
International SubFAB Research Labs (ISRL) initiative will enable an industry-wide collaborative effort. Member companies will gain access to a dedicated facility with a complete infrastructure required to operate a set of 300mm process tools to enable a science based research focusing on reliability issues, technology validation, pathfinding, materials handling and reclaim.
Ilya Zabelinsky is a globally recognized technical leader with nearly 30 years of experience in vacuum and gas abatement applications for semiconductor manufacturing. Ilya joined Intel in 1996, contributing to the startup and commissioning of Israel’s first 200mm FAB. He emerged as an operational and technical leader across Intel SubFABs worldwide.
In 2022, Ilya embarked on a mission to “bring Science to SubFAB” and founded the International SubFAB Research Labs. Ilya holds a B.Sc. in Chemical Engineering and possesses broad knowledge and vast practical experience in semiconductor manufacturing processes, FAB equipment, central facilities, and infrastructure.
International SubFAB Research Labs (ISRL) is a privately owned company founded by highly experienced and skilled team of semiconductor industry veterans.
ISRL’s vision is to fill the immense gap between industry’s desire for sustainable manufacturing and its ability to effectively address fundamental efficiency issues associated with handling, abatement and reclaim of hazardous process material waste streams. In other words – all is SubFAB.
ISRL is a first of kind facility with complete infrastructure required to operate a l fleet of 300mm process tools with versatile setup of deposition and dry etching process chambers, in high volume manufacturing-like conditions, to enable a wide range of sustainability research and development projects.
We are ENABLERS.
Our facility will enable OTHERS to help semiconductor operations work more sustainably with sharing of best practices leading to a fast and highly efficient deployment of sustainability improvements with a business model enabling clients to both reduce their costs and amplify sustainability benefits, faster time to market for breakthroughs, innovations and operational excellence in sustainable semiconductor manufacturing.
We are opening new horizons in research by understanding the significant environmental challenges that have been historically overlooked by the commercial pressures of value-generating semiconductors fabrication.
Our facility will offer a unique opportunity for companies looking to validate and qualify their equipment and technologies aimed at environmental sustainability.
We will simulate HVM-like conditions to support R&D for next generation gas abatement, materials recycle/reclaim, energy efficiency and other critical segments to enable sustainable semiconductor manufacturing in decades to come.
COO
Day 2 / 16:10 - 16:40
SVP Global Sales
Day 1 / 16:45 - 17:30
Christine Dunbar, formerly Senior Vice President of Global Sales at IQE, the leading supplier of compound semiconductor wafer products and advanced material solutions to the global semiconductor industry. Christine joined IQE in August 2022.
Christine was previously at GlobalFoundries where she held various executive roles driving GF business growth towards the October 2022 IPO. She joined GlobalFoundries in July 2015 with the IBM Microlectronics Division acquisition, as the Vice President of Product Management for the RF Business Unit.
Christine graduated from Cornell University in 1996 with a bachelor’s degree in Materials Science and Engineering and has held various engineering, technical management, and executive positions throughout her career, including leadership roles in Sales, Business Development & Semiconductor Manufacturing Operations. In 2018 Christine was nominated for the Global Semiconductor Association’s inaugural “Rising Woman of Influence” award.
Christine is passionate about serving as an ambassador for her employers and the semiconductor industry writ large thru active participation and speaking engagements at various industry forums. Christine is also a passionate advocate for women in semiconductors, and has sponsored the establishment of women’s resource groups at IBM, GlobalFoundries and IQE.
Christine is also active in her community supporting causes important to her. She is a founding member of the Leadership Now Project, a group of non-partisan business leaders committed to the health of the US democracy, established in 2017. Christine also serves on the Board of Directors at the Boys and Girls Club of Burlington, Vermont. She lives in Shelburne, Vermont USA with her partner & two teenage children.
Executive Vice President and Chief Strategy Officer
Day 1 / 11:10 - 11:30
For over 50 years, Moore’s Law has defined the pace of the semiconductor industry with its ability to scale transistor density every 2 years. While the front end roadmap is still progressing thanks to EUV lithography and other process technology innovations, it’s no longer sufficient to keep pace with the diversified demand of the new digital society.
In recent years, we have seen an acceleration of technical innovations in IC packaging and IC substrates to complement front end wafer fabrication technologies and meet performance, power, and cost requirements.
The implementation of heterogeneous integration started long ago with the first multi-chip modules and 2D packages and is now accelerating with several new 2.5 and 3D architectures serving various end-applications, including high-performance computing, mobile, and networking, among others.
With interconnect geometry scaling, we see the need and the opportunity to bridge process equipment and process control methodologies across the three worlds of front-end, packaging and substrates. These once completely separated domains are becoming integrated just like the packages and systems they create.
The adoption of front end-like technologies and methodologies into packaging and IC substrates is not trivial and it requires innovation and customization to meet cost and performance requirements.
KLA is partnering with key industry players to bridge these three worlds and this presentation will show the challenges we are facing and problems we are solving to advance the semiconductor technology roadmap.
Keywords: Innovation, Advanced Packaging, Technology Roadmap, Heterogeneous Integration, Substrates
Oreste Donzella serves as Executive Vice President and Chief Strategy Officer at KLA Corporation, leading key corporate growth initiatives and working closely with external stakeholders, such as financial investors and end customers in the broad electronics ecosystem.
Prior to his current role, Oreste was Executive Vice President, managing the Electronics, Packaging and Component (EPC) business group at KLA Corporation, which included multiple product divisions, targeting growth opportunities in specialty semiconductors, packaging, printed circuit board and display markets.
Previously, Oreste was the Chief Marketing Officer (CMO) of KLA. In this role, he oversaw corporate marketing activities, market analytics and forecast, and companywide collaborations with the broad electronics industry.
In the years before his CMO role, Oreste led the world-wide field applications engineering team, and was responsible for Customer Engagement projects and product portfolio optimization for wafer inspection platforms at KLA.
Previously, Oreste was Vice President and General Manager of the Surfscan and SWIFT divisions at KLA-Tencor. In these positions, he was responsible for the unpatterned wafer inspection, wafer geometry, and macro inspection business, overseeing new products development, sales, and marketing activities, customer support, and ultimately, division financial performance (P&L).
Oreste brings 30+ years of experience in the semiconductor industry. Prior to joining KLA in 1999, he spent almost seven years at Texas Instruments and Micron Technology, holding engineering and management positions in the process integration and yield enhancement departments.
Oreste holds various patents and is featured in several technical publications.
In 2020, Oreste was awarded with VLSI Semiconductor All Star for “charting KLA’s path into new markets related to More than Moore semiconductor technologies”
Oreste earned his master’s degree in electrical engineering from the University La Sapienza in Rome, Italy .
KLA develops industry-leading equipment and services that enable innovation throughout the electronics industry. We provide advanced process control and process-enabling solutions for manufacturing wafers and reticles, integrated circuits, packaging, printed circuit boards and flat panel displays. In close collaboration with leading customers across the globe, our expert teams of physicists, engineers, data scientists and problem-solvers design solutions that move the world forward. Additional information may be found at kla.com
CVP & GM, Advanced Packaging Customer Operations
Day 2 / 14:30 - 14:35
Despite slowdown, semiconductor industry continues to be vibrant in addressing next generation technology challenges in logic, memory, specialty devices and advanced packaging. Lam Research, a US based capital equipment leader in this ecosystem, plays key role in advancing the industry. This presentation shares Lam’s initiatives in driving the technology development to enable future semiconductor solutions. As technology advances exponentially, the big question is around how to accelerate semiconductor innovation in an ecosystem that can often be bound by physical limitations, siloed research and development efforts and the time it takes to connect. The answer will be explored in the presentation, of which Lam proposes a new concept to bring that ecosystem together like never before : through Semiverse.
Andrew is currently the Corporate Vice President and General Manager of Lam Research Southeast Asia. Since September 2018, Andrew expanded his role and leads the world-wide Advanced Packaging Customer Operations (APCO) organization. The APCO organization at Lam Research provides best-in-class technology and productivity solutions for existing and emerging advanced packaging applications.
Andrew has over 26 years of experience in the semiconductor industry and prior to Lam Research, Andrew headed the Novellus Systems SE-Asia operations as the Country Manager from 2005 to 2012.
Andrew received a bachelor’s degree in Electronic and Electrical Engineering from the University of Sheffield U.K. and has attended AIEP – Executive Program (INSEAD). Andrew also serves as the Vice Chairman of SEMI Regional Advisory Board.
Lam Research Corporation is a trusted global supplier of innovative wafer fabrication equipment and services to the semiconductor industry. Our strong values-based culture fuels our progress, and it’s through collaboration, precision, and delivery that we are driving semiconductor breakthroughs that define the next generation. Lam Research (Nasdaq: LRCX) is a FORTUNE 500® company headquartered in Fremont, California, with operations around the globe. Learn more at www.lamresearch.com
We combine superior systems engineering, technology leadership, and a commitment to customer success to advance the global semiconductor industry. Our broad portfolio of market-leading deposition, etch, strip, and wafer cleaning solutions helps customers achieve success on the wafer by enabling device features that are 1,000 times smaller than a grain of sand—it’s why nearly every chip today is built with Lam technology.
VP External Relations, Community, Government & Economic Development
Day 1 / 08:10 - 08:30
Greater Phoenix is home to an ever-expanding ecosystem of semiconductor manufacturing and its supply chain. Long-term strategic planning of resources at the state and regional level have supported this growth, ensuring that adequate water and nation-leading grid reliability meet the needs of industry. Paired with a robust workforce and an educational system anchored by Arizona State University and the Maricopa County Community College District, the region has the requisite labor force to meet the needs of key industry sectors. Greater Phoenix is a top global destination for businesses and uniquely positioned to seize the momentum of technological innovation and advanced industry to support future development.
Darcy Renfro is Vice Chancellor of Community, Government Relations, & Economic Development for the Maricopa County Community College District (MCCCD). She oversees workforce and economic development strategies for MCCCD and advises the Chancellor on government and community affairs. MCCCD is one of the largest community college systems in the nation serving approximately 200,000 students and nearly 10,000 faculty and staff members across 10 colleges in the metropolitan Phoenix area. As part of the Chancellor’s executive team, Ms. Renfro is helping to lead the Maricopa Transformation to fundamentally transform the student experience to meet the education and employment needs of the community.
Prior to her current role, Ms. Renfro served as the policy advisor to Governor Janet Napolitano for workforce, economic development, and higher education, and was founding Director of The Arizona We Want Institute at the Center for the Future of Arizona where she was responsible for strategic direction and development of a series of “Progress Meters” to establish clear metrics for Arizona in achieving its citizens’ goals. She previously worked as the founding Director of the Arizona STEM Education Network at Science Foundation Arizona.
Ms. Renfro is a licensed attorney in Arizona and has practiced at the Phoenix offices of Fennemore Craig, P.C. Prior to law school, she worked on Capitol Hill for U.S. Senators Dennis DeConcini (AZ) and Howard Metzenbaum (OH).
Ms. Renfro is a native of Tucson and received both her undergraduate and Juris Doctor Degrees from the University of Arizona.
Customer Solutions Architect, Packaging
Day 2 / 11:20 - 11:40
Wolfgang is a Distinguished Engineer in Marvell’s ASIC Business Unit. He works on advanced package solutions and chip interface definition for all ASIC products that require integration of multiple active components.
Before he started at Marvell Semiconductor, Wolfgang worked as a Packaging Engineer at IBM, and as a Customer Product Solutions Architect at Globalfoundries and at Avera Semi.
Wolfgang has authored more than 30 industry papers and publications, and holds more than 130 patents.
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you.
Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Silicon Research Director at Reality Labs
Day 2 / 11:00 - 11:20
Augmented reality is a set of technologies that will fundamentally change the way we interact with our environment. It represents a merging of the physical and the digital worlds into a rich, context aware and accessible user interface delivered through a socially acceptable form factor such as eyeglasses. One of the biggest challenges in realizing a comprehensive AR experience are the performance and form factor requiring new custom silicon. Innovations are mandatory to manage power consumption constraints and ensure both adequate battery life and a physically comfortable thermal envelope. This presentation reviews Augmented Reality and Virtual Reality applications and Silicon challenges.
Edith Beigné is the Research Director of AR/VR Silicon at Meta Reality Labs where she leads silicon research projects driving the future of AR devices. Her main research interests are low power digital and mixed-signal circuits and design with emerging technologies. Over the past 20 years, she has been focusing her research on low power and adaptive circuit techniques, exploiting new design techniques and advanced technology nodes for different applications ranging from high performance multi-processors to ultra-low power SoC, and, more recently, AR/VR applications. She was the technical chair of ISSCC 2022 and part of ISSCC TPC since 2014, she was part of VLSI symposium TPC between 2015 and 2020. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor in 2018. She visited Stanford University in 2018 to research on emerging technologies and new architectures.
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology.
CTO
Day 2 / 14:25 - 14:30
Advanced silicon wafers can greatly improve MEMS and RF device performance and precision, and they can also effectively remove some of the burden in the front-end operations.
Bonded Silicon-On-Insulator (SOI) wafers’ high degree of device layer specification flexibility and high thickness uniformity drive for improved MEMS device performance and precision, design freedom and miniaturization. The use of hermetically sealed structures enabled by Cavity SOI (C-SOI®) wafers also enable more streamlined MEMS manufacture and cost-savings.
High resistivity wafers with highly efficient trap-rich layer and optional ultra-flat wafer geometries provide optimized wafer solution even for the most demanding RF filter and device requirements. They enable RF filters to reach superior performance in terms of very low second harmonics and IMD3 levels, low insertion losses and excellent Q values.
Dr. Atte Haapalinna is chief technical officer at Okmetic, the leading supplier of advanced silicon wafers. He has published two dozen papers on various applications of advanced silicon substrates, silicon damage characterization and silicon photodetectors. Dr. Haapalinna has been with Okmetic since 1998, holding various positions including senior vice president of products, senior vice president of customer support and senior manager of new business development. He has participated in development of C-SOI® wafers, ultra-low resistivity wafers for power devices and engineered high resistivity wafers for RF filters and devices. Dr. Haapalinna received his Ph.D. at the Helsinki University of Technology (now Aalto University), Finland.
Okmetic, established in 1985, is the 7th largest silicon wafer manufacturer in the world. The company specializes in 150-200 mm silicon and SOI wafers, serving power, MEMS, and RF device industries. Okmetic is a key player in the power device sector, offering optimized silicon wafers for discrete power devices, power management applications, and GaN growth.
Okmetic has worldwide sales organization and headquarters located in Finland, where the majority of its silicon wafers is manufactured. The company’s fab expansion set to be operational in early 2025 will increase 200 mm wafer capacity significantly. Okmetic operations are certified under ISO 9001:2015, ISO 14001:2015, and IATF 16949:2016, highlighting its commitment to quality and sustainability.
Okmetic is the leading supplier of advanced, high value-added silicon wafers for the manufacture of MEMS and sensors, RF filters and devices as well as power devices. We have the most extensive 150 to 200mm wafer portfolio in the market comprising of comprehensive lines of SOI wafers and High Resistivity RFSi® wafers as well as Patterned wafers, SSP and DSP wafers, TSV wafers, Wafers for Power devices and GaN-on-Si applications.
Okmetic’s silicon wafers are tailored to the customer’s product, process and technology needs, and produced in volume production. This ensures optimum wafer performance leading to multiple customer benefits: increased device performance and functionality, more advanced design possibilities, improved yield as well as streamlined and cost-effective manufacturing. Our silicon wafer solutions can be found e.g. in smartphones, portable devices and automotive electronics, and they support applications related to industrial process control, healthcare, the Internet of Things, and power and efficiency improvement.
Chief Procurement Officer
Day 2 / 13:45 - 14:15
Nana Tseng is Chief Procurement Officer of onsemi, a leading semiconductor company rooted in the combined heritage of Motorola and Fairchild. Today, onsemi is driven to innovate intelligent power and sensing solutions focusing in automotive and industrial markets. In her role, she is directly responsible for the procurement and supply partnership strategy, manage multibillion dollar spend ranging from capital equipment, wafer start materials, wafer fab and back end direct and indirect materials, external manufacturing services and corporate services. Prior to joining onsemi, she was the Vice President of Sales at Advanced Semiconductor Engineering (ASE), the world’s largest provider of independent manufacturing services in assembly and test. Her insights on the semiconductor ecosystem and supply chain are built upon her experience working with a broad portfolio of fabless, IDMs, OEMs and EMS companies. Her passion in this industry comes from working with innovative companies committed to bring the next revolutionary technology to the market. Nana was born in Taiwan, grew up in Saudi Arabia, educated in the US, and worked extensively in SE Asia before settling back to Silicon Valley. She has an MBA from MIT Sloan School of Management, and an undergraduate degree from UC Berkeley. In her spare time, she is also very active in her community. She is currently the Vice Chair of Monte Jade West Science and Technology Association, a nonprofit organization focusing to provide mentorship, investment and technology opportunities within the Asian American community and across the Pacific.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
Director, Product Marketing, Lithography
Day 1 / 16:25 - 16:30
The “More than Moore” era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75 mm x 75 mm to 175 mm x 175 mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges for advanced IC substrates. The large package size reduces the number of units per panel, making the panel yield of paramount importance. In addition, with the increasing number of RDL layers, alignment shift per buildup step, due to the process induced substrate distortion can lead to a steady overlay drift and increase the RDL total interconnect length to a point where it exceeds the resistance specification. Solutions to these high value problems will be the subject of this talk.
For more than 35 years, Keith Best has held a range of semiconductor processing and applications positions for both device manufacturing and capital equipment companies, of which 13 years were with ASML where he held the position of Director, Applications Engineering. Most recently, Keith was Advanced Packaging Process Development Engineering Manager at SkyWater Florida. He is currently the Director of Product Marketing, Lithography, at Onto Innovation supporting the JetStep® advanced packaging lithography stepper. Keith holds a B.Sc. Honors Degree in Materials Science from the University of Greenwich, UK. He has numerous publications and holds 22 US patents in the areas of photolithography and process integration.
Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.
General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com
VP Package Engineering
Day 1 / 12:45 - 13:25
Ahmer Syed is a VP of Engineering at Qualcomm in Global Manufacturing Technology and Operations organization. He leads a global team responsible for packaging technology development, NPI, HVM deployment for 5G, mobile, IoT, Connectivity, Automotive, and Compute markets.
A 30+ years veteran of Semiconductor and electronics industry, Ahmer has extensive experience in developing advanced packaging technologies such as Flip Chip, WLCSP, FO-WLP, Package on Package (PoP), QFN, and System in Package (SiP). He has authored and contributed to more than 70 technical papers and articles on advanced packaging and reliability and has been a keynote speaker in various international conferences.
Qualcomm is the world’s leading wireless technology innovator and the driving force behind the development, launch, and expansion of 5G. When we connected the phone to the internet, the mobile revolution was born. Today, our foundational technologies enable the mobile ecosystem and are found in every 3G, 4G and 5G smartphone. We bring the benefits of mobile to new industries, including automotive, the internet of things, and computing, and are leading the way to a world where everything and everyone can communicate and interact seamlessly.
VP Packaging Technology
Day 1 / 13:55 - 14:25
As power consumption in data-centers assumes increased importance, the role packaging and package reliability plays assumes a critical role. In this presentation we will review key trends in the server market, review various package technologies, modeling techniques as well as some innovative power solutions that are being implemented in servers.
Renesas Electronics empowers a safer, smarter and more sustainable future where technology helps make our lives easier.
A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live.
CTO, Semiconductor Materials, Resonac Holdings Corporation
Day 1 / 16:15 - 16:25
Resonac has started Packaging Solution Center as new R&D center to propose one-stop solution for customers in 2018 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package in October, 2021.
2.xD and 3D packages require to connect chips and components in high density, therefore, both wiring pitch and vertical interconnect dimension must be finer and finer. At the same time, in order to achieve better performance, more and more chips are integrated together and thus the package size is increasing. To meet these requirement, we are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large 2.5D advanced package.
The presentation will cover the significance and strengths of JOINT2, and updates on research and development.
Hidenori Abe CTO for semiconductor materials, Resonac Holdings Corporation Executive director, Electronics Business Headquarters, Resonac Corporation. He is leading electronics materials R&D and strategy for semiconductor, substrate and display. Until 2023, he was the head of Electronics R&D Center and Packaging Solution Center, which is open innovation hub in advanced packaging development. I launched JOINT2, new advanced packaging consortium targeting 2.xD and 3D package in 2021.Prior to the above mission, he have been a General Manager of CMP Slurry Business Sector for three years. Before that he was a Manager of Marketing Promotion Group in Innovation Promotion Center at Hitachi Chemical (HC) for 2 years. When the career, he was promoted new R&D projects, especially targeting new business field using new technologies, and also to promote developing R&D products. As a side note, HC is one of the merged companies of Resonac. Hidenori Abe was Manager of Business Development Group in Packaging Solution Center at HC for 1 year with responsibility to promote open laboratory to partners such as customers and equipment makers, responsibility of marketing wearable related materials. Before that, he was epoxy molding compounds (EMC) engineer. During his 16 years carrier as engineer, he spent time doing responsibility of development of non-conductive carbon, green EMC, Cu wire compatible EMC, wafer level compression compounds, power module EMC and so on. His Cu wire compatible EMC development work contributed to the promotion to Cu wire conversion through several published papers. He received a master degree in chemical engineering field from Tokyo Institute of Technology, Japan and a master degree at the EMBA course from Oxford, UK.
Resonac defines its purpose as “Change society through the power of chemistry.” Resonac aims to be a world-class functional chemical manufacturer, creating functions necessary for the times, supporting technological innovation, and contributing to the sustainable development of our customers. Resonac is Global Leading semiconductor materials supplier. In order to achieve technological innovation for solving various social issues, it is essential for us to make wide-ranging co-creative efforts with partners, and Resonac is open to collaboration including 1on1 co-development with any partner.
We have opened a Packaging Solution Center and are actively engaged in next-generation semiconductor co-creation activities through JOINT2 with many partner companies. Furthermore, starting this year, we will also seek co-creation opportunities in the United States by launching US-JOINT.
Founder & CEO
Day 1 / 15:55 - 16:05
Previously we have demonstrated that electroplated copper could be engineered to have microstructures at um and nm scales. This paper shows that not all nanograined copper is created equal. Through systematic investigations, significant insight is obtained into the necessary conditions to create a stable nanograined copper that meets the following criteria: 1. microstructure stable over 9 months at ambient storage conditions, 2. textures of the electrodeposited copper do not depend on substrate types and their textures, 3. grain growth increases to micron scale at temperatures above 150 C. Furthermore, we shall introduce a concept of nanograin threshold in the context of RT microstructure stability.
Dr Yun Zhang, founder and CEO of Shinhao Materials LLC, has been active in materials innovation, R&D, marketing and sales for over 28 years, holding 34 granted patents, and numerous peer-reviewed journal publications and awards. She started her career at AT&T Bell labs in 1994, carrying out materials research and development. Her work on tin whisker growth won international recognition for demonstrating experimentally for the first time its driving force and for developing mitigation solutions. In 2002, she was appointed global R&D director by Cookson Electronics Enthone for its electronics business. In the subsequent 10 years, her insight and leadership in fundamental understanding of electrodeposition process at a molecule level, combined with a deep appreciation of technology trends and customer needs has won Dr. Zhang many friends and willing partners at top tier equipment manufacturers and key customers. Those close and collaborative partnerships resulted in win-win to all parties for RDL, copper pillar and TSV plating. She received a BS in chemistry from Nanjing University, and a PhD in chemistry from Brown University.
Shinhao Materials LLC is located in Suzhou China. Its mission is to invent and produce new materials to meet the ever-changing needs of the semiconductor industry, to service its customers in timely and cost-effective way. Being technology heavy, asset light, it has focused on technology innovation. Through its relatively short life, it has developed several unique classes of copper plating additives that have shown to be effective in addressing electrical, thermal, and stress challenges we are facing today. Its IntraCu® products are patent-protected in US, Korea, Taiwan and mainland China. In 2019, Shinhao Materials formed a strategic partnership with Umicore EP to sell and service its customers better internationally.
Head of Global Packaging
Day 1 / 12:45 - 13:25
Tony is Sr Director of Global Packaging for Skyworks Solutions. His teams lead advanced packaging R&D and production for wireless semiconductor products, including cellular, infrastructure, automotive, defense, IoT, and others.
He holds degrees in Chemical Engineering from the University of Illinois Champaign-Urbana and an MBA in Technology Management.
Skyworks Solutions, Inc. is empowering the wireless networking revolution. Our highly innovative analog semiconductors are connecting people, places and things spanning a number of new and previously unimagined applications within the automotive, broadband, cellular infrastructure, connected home, industrial, medical, military, smartphone, tablet and wearable markets.
Skyworks is a global company with engineering, marketing, operations, sales and support facilities located throughout Asia, Europe and North America.
Skyworks products are used in aerospace, automotive, broadband, cellular infrastructure, connected home, defense, entertainment and gaming, industrial, medical, military, smartphone, tablet, and wearable markets.
Senior Director of Global Industrial Engineering and Automation
Day 2 / 15:40 - 16:10
Juan is Sr Director of Global Industrial and Systems Engineering for Skyworks Solutions. He has 20 years of U.S. and international experience in semiconductor multi-site manufacturing. His experience ranges from strategic planning to data analytics that drive programs across different functional groups, business units and international sites. Recent initiatives include capacity planning for new technology introduction and the digital transformation of wafer manufacturing sites. He has a MS in Industrial and Operations Engineering from the University of Michigan and a BSEE from the University of California, Irvine.
Skyworks Solutions, Inc. is empowering the wireless networking revolution. Our highly innovative analog semiconductors are connecting people, places and things spanning a number of new and previously unimagined applications within the automotive, broadband, cellular infrastructure, connected home, industrial, medical, military, smartphone, tablet and wearable markets.
Skyworks is a global company with engineering, marketing, operations, sales and support facilities located throughout Asia, Europe and North America.
Skyworks products are used in aerospace, automotive, broadband, cellular infrastructure, connected home, defense, entertainment and gaming, industrial, medical, military, smartphone, tablet, and wearable markets.
President of Accel-RF
Day 2 / 14:15 - 14:25
Conditions are changing rapidly in today’s semiconductor manufacturing market. A convergence of emerging applications — primarily 5G, IoT, AI, and AVT— has bolstered the electronics industry. While this boom is good news for the semiconductor manufacturer, the variety of applications place pressure on companies to meet multiple benchmark reliability guidelines. Manufacturers must validate reliability performance to standards of each industry. Add to this the fact that the semiconductor market has an established history of strict reliability standards already entrenched in the markets, and companies face a seemingly impossible uphill climb to qualify their technology to meet opportunity windows.
How can the technical team arm sales and marketing with hard data to convince customers that new, un-fielded products will work in the intended environment?
Mr. Shaw is President of Accel-RF Corporation and has over 40 years’ experience in RF/microwave test system development. He is an acknowledged industry leader in developing compound-semiconductor accelerated life test methodologies, and co-authored the “Gallium-Arsenide (GaAs) MMIC Reliability Assurance Guideline for Space Applications”, released by NASA-JPL in 1996 as the “guidebook” for space qualification of Gallium-Arsenide MMICs.
Mr. Shaw previously held management and technical positions at Lockheed Martin, Texas Instruments, and was Program Manager on several key projects for NASA-JSC. He has an MSEE from Southern Methodist University (SMU) and BSEE from Texas A&M University.
STAr Technologies, established in year 2000 and headquartered in Hsinchu Taiwan, with more than 800 employees servicing customers worldwide. We provide test technologies including software, instruments, automatic test equipment, burn-in systems, probe cards, and outsourcing test services to meet demanding challenges within the semiconductor industry. Our expertise extends across parametric electrical tests (E-test), wafer-level and package-level reliability (WLR & PLR), mixed signal tests, RF and power ICs burn-in, MEMS probe cards, load boards, test interfaces and sockets.
Accel-RF Instruments and STAr-Edge Technologies, located in California, provides world leading test equipment for performing high voltage-current, and wide temperature capabilities for long-duration reliability testing and burn-in qualification of compound semiconductors, such as Gallium-Nitride (GaN) and Silicon-Carbide (SiC). These test systems have enabled successful technology developments, product launches, and industry adoption of GaN transistors and MCMs into the aerospace, military, and commercial wireless, and power electronics markets, among others.
Sales Contact Information
Phone: +1-408-416-0777
E-mail: Sales-US@STAr-Quest.com
Website: www.STAr-Quest.com
President TMEA – TEL Manufacturing and Engineering of America
Day 1 / 19:00 - 21:00
+ Industry Awards Ceremony
Mark is President and General Manager of TEL Manufacturing and Engineering of America (TMEA), a group company of Tokyo Electron Limited.
Prior to joining TEL in April 2020 he was the VP of module engineering and manufacturing operations at GLOBALFOUNDRIES Fab 8, where he led a 10X increase in manufacturing capacity, ramping production volume and yield to world class levels.
Mark spent over 20 years in IBM’s semiconductor unit, working as a process and integration engineer before holding progressively larger management responsibilities in module engineering, process control, manufacturing operations, and unit process development.
He holds a BS in Chemical Engineering from Clarkson University, where he was formerly a member of the Industry Advisory Board for the Center for Advanced Materials Processing (CAMP), and currently serves as the chair of the Dean’s Leadership Council for the Wallace H Coulter School of Engineering.
Mark and his wife Amy reside in Minneapolis, and have four children.
As a leading global company of semiconductor and flat panel display (FPD) production equipment, Tokyo Electron Limited (TEL) engages in development, manufacturing, and sales in a wide range of product fields. Building on the technological expertise and know-how that we have been cultivating since our inception over 50 years ago, we strive to contribute to the development of a dream-inspiring society. All of TEL’s semiconductor and FPD production equipment product lines maintain high market shares in their respective global segments. TEL provides outstanding products and services to customers through a global network in the U.S., Europe, and Asia.
Website: https://www.tel.com/
Phone: +1-512-424-100
Additional Contact Information: https://www.tel.com/contactus/
VP Fab Operations
Day 2 / 15:40 - 16:10
Maitreyee Mahajani is Vice President of Fab Operations at Western Digital and manages the Western Digital-Kioxia (previously Sandisk-Toshiba) JV Fabs and is also responsible for managing the NAND supply strategy for Western Digital.
Prior to joining Western Digital, Maitreyee worked at Applied Materials in various technical leadership positions. She has extensive experience developing semiconductor processing equipment which includes the very first 300mm CVD W deposition system, High K/Metal Gate systems and new ALD platforms to name a few.
As Process and Device Integration Engineer at Matrix Semiconductors (Acquired by SanDisk), Maitreyee developed many innovative ideas for building 3D Memory Devices.
Maitreyee holds a Bachelor of Engineering degree from the College of Engineering in Pune, India and a Master’s degree in Material Science from University of Alabama, Tuscaloosa. She holds over 40 patents and is a recipient of YWCA TWIN award (Tribute to Women in Industry). She is on the council for Global Semiconductor Alliance (GSA) Women Leadership Initiative and actively participates in promoting women in engineering at Western Digital and through GSA.
She is based at the company’s San Jose, CA headquarters location.
Western Digital Corporation is an American data storage company renowned for its innovative solutions. With a wide range of products including hard drives, solid-state drives, and data center solutions, Western Digital prioritizes data security and protection, consistently pushing the boundaries of storage technology to meet evolving customer needs.
End of content
End of content