07:50 – 08:30

Registration

08:35 – 08:55

ISES Welcome Address

Kamel Ait Mahiout photo

Kamel Ait Mahiout

President

Chiplet Ecosystem Acceleration: Strategy, Roadmap & Standardization

09:00 – 09:30

Keynote

Chiplet Ecosystem Acceleration

The speaker will share the work of TSMC in Chiplet Ecosystem acceleration by following outlines.

Outlines:

  • Forces Driving Chiplet and Integration
  • Advanced CMOS Technologies
  • Advanced Packaging Technologies
  • Design Enablement and Ecosystem
KC Hsu photo

K.C. Hsu

VP, Research & Development / Integrated Interconnect & Packaging

TSMC

09:30 – 10:00

Keynote

HBM (High Bandwidth Memory) and Advanced Packaging Technology for AI Era

The semiconductor packaging industry is expected to grow in the coming years, driven by the increasing demands for semiconductor chips in various applications, such as smartphones, autonomous vehicles, 5/6G, high-performance computing, IoT devices, and artificial intelligence. Another trend is the increasing adoption of heterogeneous integration, where different types of chips, such as CPUs, GPUs, and memory, are integrated into a single package to improve performance and reduce power consumption.

To overcome the limitations of performance/power/density/bandwidth of cutting edge systems, and to create new business opportunity and new values, the importance of advanced packaging technologies is more increased. For the above reasons, the future of the semiconductor packaging industry looks promising, with the increasing demand for semiconductor chips in various applications and the emergence of new packaging technologies driving growth and innovation in the semiconductor industry.

Major semiconductor players accelerate the competition to lead semiconductor industry hegemony by the evolution of advanced packaging technology such as chiplets and 2.5D/3D heterogeneous integration.

SK hynix drive the innovation of packaging technology to meet the demand for higher bandwidth and capacity of memory devices requiring in the increased AI workload applications such as the advent of ChatGPT, an artificial intelligence chatbot. High bandwidth memory (HBM), offers the largest capacity and bandwidth and also comes with the most improved power efficiency enabled by an advanced packaging technology of novel 3D chip stacking. SK Hynix is taking the lead in the HBM market. It developed the world’s first HBM in cooperation with AMD in 2013 and continuously released second/third/fourth-generation HBMs (HBM2/HBM2E/HBM3), and has secured a market share of 60-70 percent. The chip-let technology based on heterogeneous integration will be another key driver for memory-centric systems various combination of logic and memory devices. By the evolution of advanced packaging technologies, SK Hynix will continuously lead the competitiveness of memory business and prepare the business innovation for beyond memory era.

Kangwook Lee, Ph.D.

SVP and Head of PKG Development

SK Hynix

10:05 – 11:05

Networking and Coffee Break Business Meeting Slot 1&2

11:10 – 11:30

Powering the AI Revolution through Innovations in High Bandwidth Memory

Bret Street

Bret Street

Senior Director of Advanced Packaging

Micron Technology, Inc.

11:30 – 11:50

Generative AI Driven Advanced Packaging and Materials Innovation

We have seen a tremendous explosion of computational growth for generative AI. The wide range of use cases is driving innovation to grow and expand AI model complexity. This expansion is driving a continued need to innovate the computational capabilities of the generative AI processors. More compute requires more memory, more performance and more SERDES data rates. All of this requires immense power to run. New advanced packaging technology, process technology and materials are needed to ensure we have the hardware to drive the AI revolution.

Dr. Bill En photo

Dr. Bill En

CVP, Foundry Technology and Operations

AMD

Glass Substrates Manufacturing

11:50 – 12:20

Keynote

Advanced Packaging Technologies for Heterogenous Integration: Glass Core Package Substrate

(Virtual Presentation)

Rahul Manepalli, Ph.D. photo

Rahul Manepalli, Ph.D.

Intel Fellow; Director Substrate TD Module Engineering

Intel Corporation

12:25 – 13:40

Buffet Lunch

13:45 – 14:35

Panel Session: Standardization for Chiplet and Advanced Packaging

Moderator

Kuan-Neng Chen, Ph.D.

Dean/Chair Professor

NYCU

Dr. Bill En photo

Panelist

Dr. Bill En

CVP, Foundry Technology and Operations

AMD

Panelist

Walter Chen

SVP, Greater China Sales & Marketing

Amkor Technology, Inc.

Bret Street

Panelist

Bret Street

Senior Director of Advanced Packaging

Micron Technology, Inc.

Panelist

Kam Lee
Senior Director, Advanced Packaging Technology and Service

TSMC

Silicon-Photonics and Co-Packaged Optics Session

14:40 – 15:00

Heterogeneous Integration for Photonic Light Engines

Heterogeneous integration is essential for the manufacturing of higher speed, lower power and highly compact optical components. In this talk we discuss heterogeneous optical integration, where separately manufactured electronic components are assembled on to an active silicon photonics interposer. This process allows for the integration of components independently designed and optimized from several different technology and foundry platforms, including semiconductor lasers onto a common active, optical interposer.

Dr. Radha Nagarajan photo

Radha Nagarajan, Ph.D.

SVP & CTO

Marvell Technology

15:00 – 15:20

Optical I/O Technology for the Future of AI

Mark Wade, Ph.D.

CEO

Ayar Labs

15:25 – 16:25

Networking and Coffee Break Business Meeting Slot 3&4

Equipment / Materials Suppliers Update

16:30 – 16:40

Enabling Metrology, Inspection and Lithography Technologies for AI and HPC Packaging

The increasing demand for advanced applications such as artificial intelligence (AI) and high-performance computing (HPC) has driven the greater adoption of the heterogeneous integration of chiplets into advanced packaging technologies. To optimize power, performance, area, and cost for specific applications, integration is pursued at both wafer and panel levels. In this presentation we will discuss key integration technology trends and examine how Onto Innovation’s comprehensive product portfolio addresses these high-value challenges.

Monita Pau, Ph.D.

Strategic Marketing Director, Advanced Packaging

Onto Innovation

16:40 – 16:50

Wet Process and TBDB for Heterogeneous Integration

Wet process and TBDB (Temporary Bonding and Debonding) are important and critical for heterogeneous integration and advanced packaging.

Eric Lee

CEO

Scientech

16:50 – 17:00

Co-Packaged Optics and Solutions for High Volume manufacturing

The rapid development of AI, IoT, 5G and high-performance computing applications has led to exponential growth in data traffic within data centers. Nearly three-quarters of this data traffic remains within the confines of data centers. Traditional pluggable optics cannot keep up with this surge. This is where Co-Packaged Optics (CPO) technology comes into play.

CPO represents a disruptive approach to increasing bandwidth density and energy efficiency. It achieves this by significantly reducing electrical interconnect lengths through advanced packaging and simultaneously optimizing electronics and photonics. Particularly on the silicon platform, CPO holds promise for future data centers.

International companies such as Intel, Broadcom, and IBM have heavily invested in CPO technology. This interdisciplinary research field encompasses photonic devices, integrated circuit designs, packaging, modeling of photonic components, electronic-photonics co-simulation, applications, and standardization.

The challenges in CPO production are diverse. These include integrating electronics and photonics, developing reliable packaging technologies, and standardization efforts. Nevertheless, CPO offers tremendous potential for the future of data center connectivity.

ASMPT as a key equipment supplier for CPO applications offers the solutions for high volume manufacturing of Co-Packaged Optics devices.

Dr. Johann Weinhändler photo

Dr. Johann Weinhändler

Managing Director

ASMPT Limited

17:00 – 17:10

State-of-the art solutions for AI Chip manufacturing

Over the past nine months, the AI chip boom has accelerated considerably. High-bandwidth memory (HBM) chips, which are an essential part of AI chips, are undergoing rapid technological advancements. While temporary bonding will still be needed for wafer thinning of HBM3 chips and following generations, production of HBM chips is supposed to shift from thermal compression (TC) bonding to hybrid bonding solutions. TC may still be the preferred option for HBM4, as hybrid bonding is significantly more expensive. However, with HBM5 at the latest, the switch to hybrid bonding is expected to take place due to higher I/O densities. SUSS MicroTec has developed a D2W hybrid bonding solution together with flip-chip bonder specialist SET and also offers W2W hybrid bonding solutions, thus providing the technologies required for the next generations of HBM and AI chips.

Robert Wanninger photo

Robert Wanninger

Senior Vice President Business Unit Advanced Backend Solutions

SUSS

17:10 – 17:20

The Impact of PulseForge’s Photonic Debonding on Temporary Bonding and Debonding Processes

PulseForge is at the forefront of semiconductor technology innovation. This presentation highlights our flagship photonic debonding (PDB) technology and its transformative impact on Temporary Bonding and Debonding (TB/DB) processes. PDB technology utilizes broadband light (200 nm – 1100 nm) from flashlamps, paired with an engineered light-absorbing layer, to achieve superior results in wafer thinning, Fan-out, and substrate transfer applications.

As TB/DB processes become increasingly prevalent, particularly with high-bandwidth memory chips and other advanced packaging applications, our presentation provides a comprehensive assessment of PDB’s effectiveness with thinned silicon wafers. We also offer a comparative yield analysis of devices as fab-out and post-TBDB processes with photonic debonding. Furthermore, we will emphasize the substantial cost of ownership benefits that PDB offers, demonstrating clear advantages of PDB over traditional debonding processes and making it a compelling choice for semiconductor manufacturers looking to enhance performance and reduce costs.
The PDB features a uniform, large-area illumination (75 mm x 150 mm), ensuring enhanced yield, high throughput, and cost-effectiveness for both wafer-level and panel-level packaging.

Vikram Turkani

Director, Technology Partnerships and Strategic Business Development

PulseForge

17:20 – 17:30

Innovative laser assisted bonding processes for next generation advanced packaging

Conventional assembly techniques like thermo-compression bonding, oven reflow, or thermossonic wire bonding introduce high thermal and mechanical stress into the contacts and the entire semiconductor package, leading to warpage, cracks, or delamination effects. Moreover, the increasing significance of the IMC-layer becomes crucial when considering further miniaturization roadmaps of solder-based contacts << 16μm using these conventional bonding processes. To address this, “PacTech” has been developing laser-assisted processes since 1995, which enable high dynamic local and selective heating and are therefore ideal for next-generation advanced packaging. Laser-assisted reflow (LAR) of C4 bump arrays and SMD-populated substrates, laser-assisted chip bonding (LAB) and debonding processes (LAdB) as well as laser-soldered wire bonding (SB²-WB) for high-power devices, will be introduced and explained as alternative bonding solutions.

Matthias Fettke photo

Matthias Fettke

VP Advanced Packaging Equipment

PacTech

Management Consultancy Session

17:30 – 17:50

Disruptions in Semiconductor Supply Chain

a. We have been working with 3000+ global executives to reveal the level of disruption across various sectors and the driving force behind
b. The recent result shows semiconductor is experiencing more distruption than others
c. The driving forces behind are a few technology advancement, supply chain rebalancing driven geopolitical tension and customer demands
d. We have helped many of them take concrete actions to smooth the disruption from various topics
f. The key trends in supply chain rebalancing and our take-aways for TW semiconductor sectors

Michael Mo photo

Michael Mo

Partner and Managing Director

AlixPartners

17:50 – 17:55

Closing Address

Kamel Ait Mahiout photo

Kamel Ait Mahiout

President

18:15 – 18:30

Dinner Check-in on 3F Ballroom

18:30 – 21:30

Gala Dinner Sponsored by Intel

  • Advisory Board Recognition
  • Member Welcome Ceremony
  • Entertainment

18:30 – 18:35 Intel Welcome Speech

Dr. Yu-Wen Huang photo

Dr. Yu-Wen Huang

Intel Hsinchu Site Manager

Intel Corporation

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