08:00 – 08:50

Registration

09:00 – 09:15

Welcome Speech

Salah Nasri

CEO & Co-Founder

I.S.E.S.

09:20 – 09:40

Chiplets and Advanced Heterogeneous Integration

With the ever-increasing demand for computing performance for mobile, IoT, AI, Big Data and automotive applications, the need for new solutions is growing due to the slowdown of Moore’s Law and computing power solutions. Heterogeneous integration is one of the key platforms to enable higher bandwidth and density for HPC and AI systems. This presentation will discuss how chiplets and advanced heterogeneous integration are enabling next generation computing.

Dr. Terry Wu photo

Dr. Terry Wu

Director

Samsung Electronics

09:45 – 10:05

Chiplets and System Integration – Key Concepts and Implementation

In this presentation, Jianmin Li, Director of R&D at Amkor Technology – China, discusses the key concepts and implementations of chiplets and system integration. Li highlights the strong trends in chiplets and heterogeneous integration products, which offer new ways to achieve innovative product architectures while maintaining optimal Performance/Power/Area/Cost (PPAC) ratios for the future of the industry. Li emphasizes the need for advanced IC packaging capabilities to support these approaches, and notes that OSATs and Foundries are actively responding to enable this integration.

The presentation emphasizes the importance of starting with a 2D module and augmenting it with 3D as necessary for enhanced performance and differentiation. Additionally, Li mentions Amkor’s involvement as a contributor member of the UCIe™ ecosystem, which aims to define next-generation computing standards. Overall, this presentation provides valuable insights into the evolving landscape of chiplets and system integration, positioning the speaker as a seasoned professional in the field.

Jianmin Li photo

Jianmin Li

Packaging R&D Director, Amkor Technology China, Inc.

Amkor Technology, Inc.

10:05 – 10:45

Networking Break, Business Meeting

10:50 – 11:10

Heterogeneous Integration Enabled by Advanced Chiplet Packaging

With the growing demand of high performance IC, heterogeneous system integration of multiple smaller chiplets by advanced packaging technology becomes one of the major driving forces of the semiconductor industry innovation. New technologies in high bandwidth 2.5D and 3D interconnection enable complex designs implementation. Chip-Package co-design is prerequisite to meet the target performance and STCO (system-technology co-optimization) methodology is critical to advance chiplet architecture for optimal system performance.

Dr. Yang Cheng photo

Dr. Yang Cheng

Senior Director Design Service BU

JCET

11:15 – 11:35

Interconnection Define Computing: Key Technology for Next Generation Computing Paradigm Evolution

MoChen Tian photo

MoChen Tian

Founder and CEO

Kiwimoore

11:40 – 12:00

The Opportunity & Challenge of OSAT for the Coming Chiplet Integration Package

The development of semiconductor IC follows Moore’s law. Today, it has encountered great challenges, whether it’s the physical size limit or the advanced manufacturing process with huge investment costs ,and so on have formed huge pressure on the industry. Packaging is considered to be the focus of continuing semiconductor chip integration in the next decade development direction, especially in the 2.5D, 3D packaging technology brought by the chiplet concept; We see that wafer factories have made faster progress in 2.5D and 3D packaging, What are their opportunities for OSAT? What challenges will it face?

Yupeng Xu photo

Yupeng Xu

CTO

Forehope Electronic (Ningbo) Co., Ltd.

12:05 – 13:15

Networking Lunch

13:20 – 13:40

Chiplet Process Integration Based on Glass Substrate and TGV Process

The hole size can be less than 15 microns, and the metal filling capacity aspect ratio can reach 10:1. It adopts high-density intermediate layer wiring, with a minimum line width and line spacing of less than 1.5um, meeting the needs of high-density interconnections such as high-performance memory and CPU. The entire packaging body uses glass as the core layer of the intermediate layer, and uses the “RDL-First” process to flip the chip onto multiple layers of RDL wiring layers to achieve electrical interconnection. Compared with TSV, it reduces parasitic capacitance and inductance effects, reduces transmission signal delay, and can be widely used in high-frequency transmission fields.

Dr. Wenbiao Ruan photo

Dr. Wenbiao Ruan

R&D Director

Xiamen Sky Semiconductor Technology Co., Ltd.

13:45 – 14:05

Memory and Processors for Chiplet Designs

Recent application of AI drives strong demand for HPC chip, and in the latest technology, 2.5D& 3D package solution provides the best electrical performance for these type chips; In this presentation, speech will focus on the CHIPLET design challenge which focus on the HBM& Logic chip multi connection.

Simon Zhang photo

Simon Zhang

VP

Jiangsu Silicon Integrity Semiconductor Technology Co., Ltd.

Equipment and Material Supplier

14:10 – 14:30

Advanced Packaging Materials and Evaluation Platform at Resonac

An increased density of IC chips and other components to increase processing speed highly will be required for post-5G/6G systems. Therefore, there is a need for technologies that allow for high-density packaging of differing chips within a single semiconductor package.

Resonac has started Packaging Solution Center to propose one-stop solution for customers in 2019 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package.

We are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large advanced package.

Hidenori Abe

CTO, Semiconductor Materials, Resonac Holdings Corporation

Resonac Corporation

14:35 – 14:40

Deep Reactive Ion Etch – Enabling Advanced Specialty Technologies and Packaging Applications

A wide range of applications in consumer electronics, automotive electronics, IoT applications and 5G cellular communications are increasingly dependent on devices such as sensors, including MEMS, and CMOS image sensors, RF Devices, advanced power semiconductors and Bipolar-CMOS-DMOS ICs. This trend means these specialty technologies currently account for approximately 30% of all global IC demand1.

Deep reactive ion etching (DRIE), initially developed for the fabrication of MEMS devices2, has since become one of the key enabling technologies used in the fabrication of such devices as well as in advanced packaging schemes that require through silicon via (TSV) integration. At the same time, demands on the capability of the DRIE process have increased as device architectures have advanced and production has shifted to high volume manufacturing on 300mm substrates.

Lam Research’s Rapidly Alternating Process (RAP) and Syndion® DRIE tools have been well established in such high-volume manufacturing for more than two decades. Today we are focused on continued enhancement of our systems and process control methodologies in order to meet future requirements.

In this work we show how development of our deep silicon etch hardware and process capabilities is resulting in significant improvements in on-wafer results and supporting next generation device fabrication. Such challenges include the continuous improvement of process productivity, improved profile control, achieving smoother etched sidewalls, and improving uniformity of both etch depth and feature CD.

To illustrate this, we will discuss critical applications such as advanced deep trench isolation (DTI) in CMOS image sensors, etching of power device trenches and TSV fabrication.

1. IC Insights, McClean Report, Feb 2022

2. Franz Laermer and Andrea Schilp, Robert Bosch GmbH, Method of anisotropically etching silicon, United States Patent 5501893

Dr. David Haynes

VP Strategic Marketing

Lam Research Corporation

14:45 – 14:50

Tailored Solutions for the Semiconductor Industry Powered by TRUMPF

With short introduction of TRUMPF and short video show how we active in Semiconductor industry, Mr. Czaja will Define our tailored solutions for customers in the semiconductor industry around the world.

Dariusz Czaja photo

Dariusz Czaja

Managing Director of TRUMPF Huettinger Asia

TRUMPF Huettinger

14:55 – 15:00

Pushing the Boundaries of Thermal Management to Address Challenges in Wafer Test and Advanced Packaging

In today’s rapidly evolving technology landscape, the semiconductor industry is constantly pushing the boundaries of innovation to meet the demands of increasingly complex systems. With the popularity of Artificial Intelligence and high demand for new power management, the importance of thermal management cannot be overstated.

As semiconductor devices shrink in size and complexity increases, they generate higher power densities, resulting in elevated operating temperatures. This poses critical wafer testing challenges for manufacturers in terms of temperature accuracy and uniformity, as even minor thermal deviations can significantly impact the performance and reliability of these advanced chips.

This presentation will introduce ERS’s latest developments in wafer probing and advanced packaging; two critical areas that are geared towards maximizing yield and guaranteeing performance.

Laurent Giai-Miniet photo

Laurent Giai-Miniet

CEO

ERS electronic GmbH

15:05 – 15:45

Networking Break, Business Meeting 

15:50 – 16:35

Focusing on the Collaboration and Leverage between UCIe and China Chiplet Standards

Prof. Qinfen Hao photo

Moderator

Prof. Qinfen Hao

Professor

Institute of Computing Technology, Chinese Academy of Science

Haopeng Liu photo

Panelist

Haopeng Liu

Technical Solution VP

AkroStar Technology Co., Ltd.

Dr. Fengze Hou photo

Panelist

Dr. Fengze Hou

Associate Professor

Institute of Microelectronics of the Chinese Academy of Sciences

Kaisheng Ma photo

Panelist

Kaisheng Ma

Chief Scientist

Polar Bear Tech

Market Research

16:40 – 17:00

Memory and Processors for Chiplet Designs

The rise of generative AI applications and high-performance computing (HPC) in data centers has boosted demand for high-speed memory and computing devices with low-latency interfaces. In this context, heterogeneous integration and chiplet architectures enabled by advanced packaging approaches (e.g., hybrid bonding) are being regarded as the most promising solutions to address the memory-bandwidth bottleneck and increase the performance of computing systems via a tight integration of logic and memory functions.

This talk will provide an overview on the interplay between memory and processors in terms of technology and markets trends, describing the main solutions, the challenges, and the opportunities ahead for semiconductor players.

Simone Bertolazzi, PhD. photo

Simone Bertolazzi, PhD.

Principal Technology & Market Analyst

Yole Intelligence

17:05 – 17:10

Closing Remarks

17:15 – 18:25

Networking Reception

18:30 – 20:30

Gala Dinner and Appreciation Award Ceremony

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