For decades, Moore’s Law has delivered the ability to integrate an exponentially increasing number of devices in the same silicon area at a roughly constant cost. This has enabled tremendous levels of integration, where the capabilities of computer systems that previously occupied entire rooms can now fit on a single integrated circuit. Although traditional scaling has slowed over the past decade, we have made tremendous progress as an industry with new approaches including chiplet-based architectures, domain-specific accelerators, and advanced packaging technologies which have enabled major milestones including the first exascale supercomputers. As we look into the future, we need to accelerate the pace of innovation to drive the next decade of advancement in high-performance computing. By far, the largest limiting factor to delivering continued compounded growth in computation power is energy efficiency. In this paper, we highlight a holistic strategy for accelerating innovation in energy efficiency required for next-generation high-performance computing and ultimately achieving zettascale performance.

Over the last several decades, systems have focused on innovation in the logic and have strayed away from ‘balanced’ machines. As a result, a significant

number of applications have been unable to leverage the additional computational power of the latest generation machines . The machine architectures need to evolve: new systems architectures and innovations require a deep understanding of the applications. Memory will be the ‘cornerstone’ of future innovative systems, which will generate a faster time to solution in a much more energy constrained envelope.

With the development of 3DIC and associated packaging technologies, semiconductor industry has extended performance and density optimization to system level, complementary to traditional chip scaling. Amid broader adoption of TSMC’s advanced 2.5D/ 3D packaging solutions along with growing chiplet complexity and form factor, the interaction between Si, packaging and components become increasingly crucial and requires continue innovations on design, process development and manufacturing.

With 3DFabric Alliance, we are extending OIP collaboration to packaging/ testing and working with industry partners on substrate and memory technology development for integrated system-level design solution to customers, together with the ecosystem of OSATs, material and equipment suppliers. In parallel, we also establish the worldwide first fully automated factory to offer best flexibility for our customers to optimize their packaging solution with better cycle time and quality control.

Today’s era of smartphones, 5G, AI and big data calls for increasingly faster speeds of computing performance. However, the speed of semiconductor innovation and technology advancement has slowed down, and chip miniaturization has reached physical limits, which has caused the speed at which transistors are growing smaller to slow down. In other words, we are now falling behind Moore’s Law.

Advances in heterogeneous chip packages are need to empower today is the device manufacturers to pursue tomorrow’s breakthrough. Both 2.5D and 3D will be needed to keep innovation vibrant also higher bandwidths and density solution is important for HPC and AI systems. So memory coherency and low latency attributes across converged compute infrastructures with interconnect technologies including UCIe.

In this paper, advanced package solutions are to be introduced and discussed in terms of challenges and opportunities for emerging high end computing, memory and mobile platforms.

Heterogeneous Integration (HI) is now one of key semiconductor worldwide trends and developing important impact and increasing influence to chip designer, Fab, OSAT, OEM/ODM and entire supply-chain enablers. The view on impact and influence can be pretty different to mobile, IoT, HPC, and automotive applications’ system developers based on various HI solutions. This presentation will discuss the HI packaging as a new enabling energy for semiconductor migration.

This keynote will explore the impact of deep learning including large language models on the semiconductor test. We will highlight the opportunities these models present for real-time data processing and discovery of insights, with specific applications in computer vision and natural language processing. However, the use of these models also introduces new security risks, particularly regarding the use of cloud infrastructure for collection of data, training and inference. By examining past attacks on networks, we will discuss the potential for malicious actors to steal data or intellectual property from companies. Attendees will gain an understanding of the opportunities and challenges in AI and security for the coming years and the importance of considering security measures in the development and deployment of these advanced solutions.

Hybrid bonding allows semiconductor wafers or individual die to be bonded with exceptionally fine-pitch (scalable to 1 micron) 3D electrical interconnects at low temperature without pressure or adhesives. Hybrid bonding was invented by a company called Ziptronix which was later acquired by Adeia (formally known as Xperi) in 2015. Since then, Adeia has continued to invest heavily in hybrid bonding R&D and supply chain enablement for production worthy wafer-to-wafer and die-to-wafer hybrid bonding processes. Adeia, a pioneer in hybrid bonding, has licensed numerous semiconductor companies to the bonding portfolio including Sony, SK hynix, Samsung, Micron, Kioxia, Western Digital, Qorvo, Canon, LAPIS, and UMC. Several of these companies engaged in a technology transfer program as well. Hybrid bonding technology was commercially adopted in stacked BSI image sensors, stacked 3D NAND memories, logic processors, and is anticipated to be adopted soon in HBM and RF front-end devices. In logic applications, a large die can be disaggregated into separate functions such as cache memory and processor. After disaggregation, the functional chiplets can be bonded on top of a core processor die to create a fully functional circuit. The hybrid bonding technology is a must-have tool to provide a multi-generational roadmap of products in high performance computing devices such as CPU, GPU, FPGA, SoC, other logic, memories, and 3D chiplet integrations.

Driven by evolving consumer preferences and regulatory pressure, it’s a consensus that the adoption of electric vehicles will continue its sharp growth trajectory in the coming years. Leading automakers and suppliers have announced rigorous investments and visionary plans to meet the booming demand. Driven by the need for longer ranges and more efficient charging capacity, EV power electronics undergo a paradigm shift toward wide bandgap semiconductors. With mature manufacturing capacity and proven reliability, GaN is changing the game for 400V and 800V EV applications by delivering unprecedented benefits in power density and even BoM cost with superior switching frequency and loss performance.

In addition, electric micro-mobility is gaining traction worldwide as it provides a greener, less expensive, and more flexible last-mile transportation option in urban areas. For applications where small size is critical, GaN has turned a new page for power electronics in two-wheeler, three-wheeler, and microcar applications.

Stephen Coates, General Manager (Asia) and VP of Global Operation of GaN Systems will address how GaN is widening its applications and making disruptive innovations in the future of mobility.

For years, the logistics industry has been challenged by its reliance on manual processes from order placement and tracking to delivery.Recent global disruptions such as COVID-19 and labor strikes have made shipping more and more difficult, but Airspace excels in the most challenging circumstances.You cannot rely on traditional logistics anymore.Airspace has built a shipping platform that’s powered by proprietary AI technology. With mobile and desktop functionality, Airspace has offered major companies in the semiconductor industry the most reliable shipping options and full visibility along the way. By calculating millions of routes for you in seconds, your most critical shipments can get there faster and more efficiently than you ever thought possible.

As the pace of Moore’s law slows, and the associated development cost increases, the industry has turned to advanced packaging to enable the improvement of the overall system performance, whilst also reducing cost. A key trend is the adoption of a “chiplet” approach, with panel level packaging and hybrid bonding being the two key advanced packaging enablers for the heterogenous integration. In this presentation, we will discuss the challenges and solutions for process control as well as the importance of chiplet genealogy.

“More Than Moore” with heterogeneous integrated Chiplets in different Advanced Packaging Architectures are continuously being developed in our Industry.

Along the development of these Advanced Packaging Architectures with the objectives of delivering the same or even better device performance as if it is in System On Chip (SOC), while at the same time of achieving the best cost of making, it brings challenges to advanced packaging engineer. ASMPT, being the total interconnect solution provider, has determined to collaborate with our customers and partners to overcome these challenges and offer the best-in-class interconnect equipment solutions to address their needs in a timely manner.

ASMPT is aiming to be a Total Interconnect Solution supplier establishing the widest product portfolio in Advanced Packaging Technology, from with thin film interconnect, to first level (die to wafer & substrate) as well as broad level interconnect (package to PCB). I am happy to share more with this presentation.

In our digital-driven society the increasing importance of information, automation and hence data processing requires the next generation of faster and smaller semiconductor devices. Metallization processes play a crucial role in enabling the newest interconnects and are hence of high importance for further technological advances. Requirements such as reliability, functionality and downsizing are thus common targets of semiconductor devices as well as plating processes.

We will present some of MKS Atotech’s new solutions for advanced packaging, such as Cu-to-Cu direct bonding as well as new processes for SnAg solder bump plating. Additionally, we will give insights into our offerings for highly reliable Si- and SiC-based Power Semiconductors.

Replacing traditional solder based micro-bump interconnects with Hybrid Bonding process flows is still considered a game changer for 3D integration. This interconnect method offers a unique solution for contact pitch scaling and therefore is in the spotlight of R&D roadmaps at all major research institutions, IDMs and foundries as well as the equipment and materials industry. In order to ensure optimum overlay results to allow for small interconnect pitches, the best possible alignment accuracy and repeatability needs to be consistently maintained during the joining process. Depending on the specific application there are different processing schemes for Hybrid Bonding which co-exist. These include wafer to wafer (W2W), collective die to wafer (CoD2W) as well as sequential die to wafer (D2W) approaches which all need to be carried out at cleanliness levels that are comparable to front-end-of-line (FEOL) requirements. Each of these process flows comes with specific challenges which need to be addressed from an equipment as well as a process perspective. SUSS MicroTec leverages its leading position in wet processing and precision alignment for wafer level processes and has partnered with SET (Smart Equipment Technology), who is one of the technology leading flip-chip bonder manufacturers. SUSS MicroTec looks back at many years of hybrid bonding co-optimization activities with the research partner imec for collective D2W, while SET has worked for many years with CEA Leti on sequential D2W. Our solutions are optimized based on the learnings from these activities. In order to ensure optimum yield it is essential to monitor the overlay results with no blind spots across the wafer. Therefore a high throughput metrology system has been developed at SUSS MicroTec, which can be used for in-line inspection to trigger control loops and to record quality data for all dies on the wafer. Stand-alone metrology solutions with multiple overlay verification modules allow customers to scale their measurement capabilities according to their manufacturing needs. Specific state-of-the art alignment and overlay results for both, integrated W2W and D2W Hybrid Bonding schemes will be reviewed.

A wide range of applications in consumer electronics, automotive electronics, IoT applications and 5G cellular communications are increasingly dependent on devices such as sensors, including MEMS, and CMOS image sensors, RF Devices, advanced power semiconductors and Bipolar-CMOS-DMOS ICs. This trend means these specialty technologies currently account for approximately 30% of all global IC demand¹.

Deep reactive ion etching (DRIE), initially developed for the fabrication of MEMS devices², has since become one of the key enabling technologies used in the fabrication of such devices as well as in advanced packaging schemes that require through silicon via (TSV) integration. At the same time, demands on the capability of the DRIE process have increased as device architectures have advanced and production has shifted to high volume manufacturing on 300mm substrates.

Lam Research’s Rapidly Alternating Process (RAP) and Syndion® DRIE tools have been well established in such high-volume manufacturing for more than two decades. Today we are focused on continued enhancement of our systems and process control methodologies in order to meet future requirements.

In this work we show how development of our deep silicon etch hardware and process capabilities is resulting in significant improvements in on-wafer results and supporting next generation device fabrication. Such challenges include the continuous improvement of process productivity, improved profile control, achieving smoother etched sidewalls, and improving uniformity of both etch depth and feature CD.

To illustrate this, we will discuss critical applications such as advanced deep trench isolation (DTI) in CMOS image sensors, etching of power device trenches and TSV fabrication.

1. IC Insights, McClean Report, Feb 2022
2. Franz Laermer and Andrea Schilp, Robert Bosch GmbH, Method of anisotropically etching silicon, United States Patent 5501893

HPC (High Performance Computing) is a powerful tool that can be applied to solve intricate problems and overcome obstacles in diverse areas such as life science , environmental sciences, industrial and finance. To achieve high computing power, cutting-edge system-on-chips (SOCs) or next generation advanced packaging technologies are utilized to integrate processors, memory, and storage either on a die or package level. However, a critical hurdle in this process is effectively managing heat to preserve computing performance and power efficiency. In this context, we will discuss the challenges and present latest progress in thin film deposition of a solderable layer stack deposition on the wafer backside (BSM) to allow a perfect, reliable connection to the thermal interface material (TIM) foil. This back side metal (BSM) layer stack has not only to meet excellent adhesion and solderability, but also minimum film stress requirements and compatibility to tight process temperature restrictions of molded substrates.