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Greater Phoenix: Semiconductor Excellence on the Global Stage
Chris Camacho
President & CEO
Greater Phoenix Economic Council (GPEC)
Advanced Packaging: Navigating System Technology Co-optimization & Embracing Innovation
Ann Kelleher, Ph.D.
EVP & GM Technology Development
Intel Corporation
CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Update
Dan Berger
Associate Director
CHIPS for America R&D Office
HPC, AI, Chiplets, heterogeneous integration
Mark Fuselier
SVP Technology & Product Engineering
AMD
Optimizing Interconnect Density with New Packaging Technologies
Oreste Donzella
Executive Vice President and Chief Strategy Officer
Silicon Manufacturing and Packaging at MSFT in the Cloud/AI era
Sriram Srinivasan
Partner Silicon Packaging Technology
Microsoft
Optimizing Cost and Quality Through Test Mobility Across Insertions
Rick Burns
President Semiconductor Test Division
Teradyne
Challenges to enabling the transition from organic to glass core substrates as RDL approaches 2 µm l/s and beyond
Keith Best
Director, Product Marketing, Lithography
Onto Innovation
Co-Packaged Optics and Solutions for High Volume manufacturing
Dr. Johann Weinhändler
Managing Director
ASMPT Semiconductor Solutions
Glass Substrates for Advanced Packaging
Dr. Xavier Lafosse
Commercial Technology Director, Advanced Optics
Corning Incorporated
Panel Discussion: Marking the Memory Wall a Memory: Prespectives on Technical and Economic Challenges
Dr. Ravi Mahajan
Intel Fellow, Assembly and Packaging Technology Pathfinding
Intel Corporation
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